參數(shù)資料
型號: PCK2057DGG
廠商: NXP SEMICONDUCTORS
元件分類: 時鐘及定時
英文描述: 70 - 190 MHz I2C differential 1:10 clock driver
中文描述: PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝: PLASTIC, TSSOP-48
文件頁數(shù): 8/12頁
文件大?。?/td> 95K
代理商: PCK2057DGG
Philips Semiconductors
Product data
PCK2057
70 – 190 MHz I
2
C differential 1:10 clock driver
2001 Jun 12
8
AC CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
MIN
TYP
MAX
t
PD
t
PHL
t
en
t
dis
t
jit(per)
t
jit(cc)
t
jit(hper)
Propagation delay time
Test mode/CLK to any output
3.7
500
1
ns
HIGH-to-LOW level propagation delay time
SCL to SDA (acknowledge)
ns
Output enable time
Test mode/SDA to Y output
85
ns
Output disable time
Test mode/SDA to Y output
35
ns
Jitter (period); see Figure 4
100 MHz to 167 MHz
–75
75
ps
Jitter (cycle-to-cycle); see Figure 5
100 MHz to 167 MHz
–75
75
ps
Half-period jitter; see Figure 6
100 MHz to 167 MHz
–90
90
ps
t
Static phase offset; see Figure 1
133 MHz/V
ID
on CLK = 0.71 V
167 MHz/V
ID
on CLK = 0.71 V
terminated with 120
/14 pF
220
450
ps
140
270
ps
t
slr(o)
t
sk(o)
Output clock slew rate; see Figure 3
1
2
V/ns
Output skew; see Figure 2
75
ps
SSC modulation frequency
30
33.3
kHz
SSC clock input frequency deviation
0.00
–0.50
%
NOTE:
1. This time is for a PLL frequency of 100 MHz.
AC WAVEFORMS
SW00882
t
(O)
=
Σ
1
n =N
t
(O)n
N
t
(O)n
t
(O)n + 1
(N is a large number of samples)
CLK
CLK
FB
IN
FB
IN
Figure 1. Static phase offset
SW00883
t
sk(O)
Yx
Yx
Yx, FB
OUT
Yx, FB
OUT
Figure 2. Output skew
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