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參數(shù)資料
| 型號(hào)： | PCK2057DGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 70 - 190 MHz I2C differential 1:10 clock driver |
| 中文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | PLASTIC, TSSOP-48 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 95K |
| 代理商： | PCK2057DGG |
Philips Semiconductors
Product data
PCK2057
70 – 190 MHz I
2
C differential 1:10 clock driver
2001 Jun 12
4
I
2
C ADDRESS
1
1
0
1
0
0
1
su01394
R/W
I
2
C CONSIDERATIONS
I
2
C has been chosen as the serial bus interface to control the PCK2057. I
2
C was chosen to support the JEDEC proposal JC-42.5 168 Pin
Unbuffered SDRAM DIMM. All vendors are required to determine the legal issues associated with the manufacture of I
2
C devices.
1) Address assignment: The clock driver in this specification uses the single, 7-bit address shown below. All devices can use the address if only
one master clock driver is used in a design. The address can be re-used for the CKBF device if no other conflicting I
2
C clock driver is used in
the system.
The following address was confirmed by Philips on 09/04/96.
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
0
NOTE:
The R/W bit is used by the I
2
C controller as a data direction bit. A ‘zero’ indicates a transmission (WRITE) to the clock device. A ‘one’
indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller to WRITE data; the
R/W bit of the address will always be seen as ‘zero’. Optimal address decoding of this bit is left to the vendor.
2) Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality required. Fast mode (400 kbits/s) functionality is optional.
3) Logic Levels: I
2
C logic levels are based on a percentage of V
DD
for the controller and other devices on the bus. Assume all devices are
based on a 3.3 Volt supply.
4) Data Byte Format: Byte format is 8 Bits as described in the following appendices.
5) Data Protocol: To simplify the clock I
2
C interface, the clock driver serial protocol was specified to use only block writes from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. Indexed bytes are not allowed. However, the SMBus controller has a more specific format than the generic I
2
C protocol.
The clock driver must meet this protocol which is more rigorous than previously stated I
2
C protocol. Treat the description from the viewpoint of
controller. The controller “writes” to the clock driver.
SW00911
1 bit
7 bits
1
1
8 bits
1
Start bit
Slave Address
R/W
DUMMY
DUMMY
Ack
Data Byte 1
Ack
Data Byte 2
Ack
Stop
Ack
Ack
1 bit
8 bits
1
1
8 bits
1
NOTE:
The acknowledgement bit is returned by the slave/receiver (the clock driver).
6) Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in section 15 of the I
2
C
specification.
a) Pull-Up Resistors: Any internal resistors pull-ups on the SDATA and SCLOCK inputs must be stated in the individual datasheet. The use of
internal pull-ups on these pins of below 100 k
is discouraged. Assume that the board designer will use a single external pull-up resistor for
each line and that these values are in the 5–6 k
range. Assume one I
2
C device per DIMM (serial presence detect), one I
2
C controller, one
clock driver plus one/two more I
2
C devices on the platform for capacitive loading purposes.
(b) Input Glitch Filters: Only fast mode I
2
C devices require input glitch filters to suppress bus noise. The clock driver is specified as a standard
mode device and is not required to support this feature.
For specific I
2
C information, consult the Philips I
2
C Peripherals Data Handbook IC12 (1997).
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