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參數(shù)資料
| 型號(hào)： | PCK2023DGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | CK408 66/100/133/200 MHz spread spectrum differential system clock generator |
| 中文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-364-1, TSSOP-56 |
| 文件頁數(shù)： | 12/30頁 |
| 文件大?。?/td> | 177K |
| 代理商： | PCK2023DGG |
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Philips Semiconductors
Product data
PCK2023
CK408 (66/100/133/200 MHz) spread
spectrum differential system clock generator
2001 Sep 07
12
ALL OUTPUTS
SYMBOL
PARAMETER
LIMITS
T
amb
= 0 to +70
°
C
MIN
1.0
UNITS
NOTES
MAX
10.0
t
PZL
/t
PZH
t
PZL
/t
PZH
t
STABLE
output enable delay (all outputs)
ns
output disable delay (all outputs)
1.0
10.0
ns
all clock stabilization from power-up
—
3
ms
11
NOTES:
1. Measured at crossing points or where subtraction of CLK-CLK crosses 0 V.
2. Measured from V
OL
= 0.175 V to V
OH
= 0.525 V.
3. These crossing points refer to only crossing points containing a rising edge of a CPU output (as opposed to a CPU output).
4. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
5. Measured from V
= 0.2 V to V
OH
= 0.8 V.
6. Determined as a fraction of 2* (t
–t
FALL
)/(t
RISE
+t
FALL
).
7. Test load is R
= 33.2
, R
= 49.9
.
8. Period, jitter, offset and skew measured at rising edge @ 1.5 V for 3.3 V clocks.
9. T
HIGH
is measured at 2.4 V for non-CPU outputs.
10.T
LOW
is measured at 0.4 V for all outputs.
11. The time specified is measured from when V
DDQ
achieves its normal operating level (typical condition V
DDQ
= 3.3 V) until the frequency
output is stable and operating within specification.
12.The 3.3 V clock t
RISE
and t
FALL
are measured as a transition through the threshold region V
OL
= 0.4 V and V
OH
= 2.4 V (1 mA) JEDEC
specification.
13.The average period over any 1
μ
s period of time must be greater than the minimum specified period.
14.Designed for 150–420 ps (1 V/ns minimum rise time across 0.42 V).
15.Measurement taken from differential waveform.
16.Measurement taken from differential waveform from –0.35 to +0.35 V.
17.Measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86 V. Rise/fall time matching is defined as “the
instantaneous difference between maximum CLK rise (fall) and minimum CLK fall (rise) time, or minimum CLK rise (fall) and maximum CLK
fall (rise) time”. This parameter is designed for waveform symmetry.
18.Measured in absolute voltage, single ended.
19.Cycle-to-cycle jitter measurements taken with minimum capacitive loading on non-CPU outputs.
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