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參數(shù)資料
| 型號： | PCK2022RDGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | CK00 100/133 MHz spread spectrum differential system clock generator |
| 中文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, SOT-362-1, TSSOP-48 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大小： | 102K |
| 代理商： | PCK2022RDGG |
Philips Semiconductors
Product specification
PCK2022R
CK00 (100/133 MHz) spread spectrum differential
system clock generator
2000 Nov 13
9
REF clock output
T
amb
= 0
°
C to +70
°
C; lump capacitance test load = 20 pF
LIMITS
SYMBOL
PARAMETER
48 MHz MODE
MIN
14.318
30
30
UNITS
NOTES
MAX
f
Frequency, actual
REFCLK LOW time
REFCLK HIGH time
Cycle-to-cycle jitter
Output duty cycle
MHz
ns
ns
ps
%
17, 20
20
20
18, 20
18, 20
t
HKL
t
HKH
t
JITTER
37
37
300
55
DUTY CYCLE
REFER TO NOTES ON PAGE 9.
45
All outputs
T
amb
= 0
°
C to +70
°
C
LIMITS
SYMBOL
PARAMETER
133 MHz MODE
MIN
1.0
1.0
100 MHz MODE
MIN
1.0
1.0
UNITS
NOTES
MAX
10.0
10.0
3
MAX
10.0
10.0
3
t
PZL
, t
PZH
t
PZL
, t
PZH
t
STABLE
REFER TO NOTES ON PAGE 9.
Output enable delay (all outputs)
Output disable delay (all outputs)
All clock stabilization from power-up
ns
ns
ms
20
20
7, 20
Group offset limits
GROUP
OFFSET
MEASUREMENT LOADS
(LUMPED)
MEASUREMENT POINTS
NOTES
Host to IOCLK
1.5 – 3.5 ns
Host leads
IOCLK @ 30 pF
Host @ Cross point
IOCLK @ 1.5 V
19, 20
NOTES TO THE AC TABLES:
1. Output drivers must have monotonic rise/fall times through the specified V
OL
/V
OH
levels.
2. Period, jitter, offset, and skew measured on rising edge at 1.5 V for 3.3 V clocks.
3. The IOCLK clock is the Host clock divided by 4 in 33 MHz mode and divided by 2 in 66 MHz mode at Host = 133 MHz.
IOCLK clock is the Host clock divided by 3 in 33 MHz and divided by 2/3 in 66 MHz mode at Host = 100 MHz.
4. Frequency accuracy of 48 MHz must be +167 ppm to match USB default.
5. t
HKH
is measured at 2.4 V for 3.3 V outputs, as shown in Figure 7.
6. t
HKL
is measured at 0.4 V for all outputs as shown in Figure 7.
7. the time is specified from when V
DDQ
achieves its normal operating level (typical condition V
DDQ
= 3.3 V) until the frequency output is stable
and operating within specification.
8. t
and t
are measured as a transition through the threshold region V
= 0.4 V and V
= 2.4 V (1 mA) JEDEC specification.
9. The average period over any 1
μ
s period of time must be greater than the minimum specified period.
10.Calculated at minimum edge rate (1 V/ns) to guarantee 45–55% duty cycle. Pulse width is required to be wider at faster edge rate to ensure
duty specification is met.
11. Test load is R
S
= 33.2
, R
P
= 49.9
.
12.Must be guaranteed in a realistic system environment.
13.Configured for V
OH
= 0.71 V in a 50
environment.
14.Measured at crossing points.
15.Measured at 20% to 80%.
16.Determined as a fraction of 2*(t
RP
– t
RN
) / (t
RP
+ t
RN
), where t
RP
is a rising edge, and t
RN
is an intersecting falling edge.
17.Frequency generated by crystal oscillator
18.Voltage measure point (V
M
= 1.5 V). V
DD
= 3.3 V.
19.All offsets are to be measured at rising edges.
20.Parameters are guaranteed by design.
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