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參數(shù)資料
| 型號： | PCK2000DL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | CK97 66/100MHz System Clock Generator |
| 中文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 7.50 MM, PLASTIC, SSOP-48 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 90K |
| 代理商： | PCK2000DL |
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
1998 Sep 29
8
AC CHARACTERISTICS
VDDREF = VDDPCI (0–1) = VDD48MHz = 3.3V
±
5%; VDDAPIC = VDDCPU (0–1) = 2.5V
±
5%; f
crystal
= 14.31818 MHz
CPU CLOCK OUTPUTS, CPU(0–3) (LUMP CAPACITANCE TEST LOAD = 20pF)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
T
amb
= 0
°
C to +70
°
C
MIN
15.0
5.2
5.0
10.0
3.0
2.8
0.4
0.4
UNIT
NOTES
2
1, 5
1, 5
2
1, 5
1, 5
9
9
MAX
15.5
T
HKP
(t
P
)
T
HKH
(t
H
)
T
HKL
(t
L
)
T
HKP
(t
P
)
T
HKH
(t
H
)
T
HKL
(t
L
)
T
HRISE
(t
R
)
T
HFALL
(t
F
)
T
JITTER
(t
JC
)
DUTY CYCLE (t
D
)
T
HSKW
(t
SK
)
T
HSTB
(f
ST
)
CPUCLK period
CPUCLK HIGH time
CPUCLK LOW time
CPUCLK period
CPUCLK HIGH time
CPUCLK LOW time
CPUCLK rise time
CPUCLK fall time
CPUCLK jitter
Output Duty Cycle
CPU Bus CLK skew
CPUCLK stabilization from Power-up
66MHz
ns
10.5
100MHz
ns
1.6
1.6
175
55
175
3
ns
ns
ps
%
ps
ms
1
2
7
45
PCI CLOCK OUTPUTS, PCI(0–7) (LUMP CAPACITANCE TEST LOAD = 30pF)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
T
amb
= 0
°
C to +70
°
C
MIN
30.0
UNIT
NOTES
3
8
1
1
10
10
2
2, 4
7
MAX
T
PKP
(t
P
)
T
PKPS
T
PKH
(t
H
)
T
PKL
(t
L
)
T
HRISE
(t
R
)
T
HFALL
(t
F
)
T
PSKW
(t
SK
)
T
HPOFFSET
(t
O
)
T
PSTB
(f
ST
)
PCICLK period
PCICLK period stability
PCICLK HIGH time
PCICLK LOW time
PCICLK rise time
PCICLK fall time
PCI Bus CLK skew
CPUCLK to PCICLK Offset
PCICLK stabilization from Power-up
ns
ps
ns
ns
ns
ns
ps
ns
ms
500
12.0
12.0
0.5
0.5
2.0
2.0
500
4.0
3
1.5
APIC(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
T
amb
= 0
°
C to +70
°
C
MIN
UNIT
NOTES
MAX
f
Frequency, Actual
Frequency generated
by Crystal
14.31818
MHz
T
HRISE
(t
R
)
T
HFALL
(t
F
)
DUTY CYCLE (t
D
)
T
HSTB
(f
ST
)
Output rise edge rate
Output fall edge rate
Duty Cycle
1
1
45
4
4
55
3
ns
ns
%
ms
Frequency stabilization from Power-up (cold start)
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相關(guān)代理商/技術(shù)參數(shù) |
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| PCK2000DL-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
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