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參數(shù)資料
| 型號(hào)： | PCK2000 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | CK97 (66/100MHz) System Clock Generator(CK97 (66/100MHz) 系統(tǒng)時(shí)鐘發(fā)生器) |
| 中文描述： | CK97（66/100MHz）系統(tǒng)時(shí)鐘發(fā)生器（CK97（66/100MHz）系統(tǒng)時(shí)鐘發(fā)生器） |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 90K |
| 代理商： | PCK2000 |
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
1998 Sep 29
9
REF(0–2) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
T
amb
= 0
°
C to +70
°
C
MIN
UNIT
NOTES
MAX
f
Frequency, Actual
Frequency generated
by Crystal
14.31818
MHz
T
HRISE
(t
R
)
T
HFALL
(t
F
)
DUTY CYCLE (t
D
)
T
HSTB
(f
ST
)
Output rise edge rate
Output fall edge rate
Duty Cycle
1
1
45
4
4
55
3
ns
ns
%
ms
Frequency stabilization from Power-up (cold start)
48MHZ(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
T
amb
= 0
°
C to +70
°
C
MIN
UNIT
NOTES
MAX
f
Frequency, Actual
Determined by PLL
divider ratio
(48.008 – 48)/48
48.008
MHz
f
D
Devation from 48MHz
Output rise edge rate
Output fall edge rate
Duty Cycle
+167
ppm
ns
ns
%
ms
T
HRISE
(t
R
)
T
HFALL
(t
F
)
DUTY CYCLE (t
D
)
T
HSTB
(f
ST
)
1
1
45
4
4
55
3
Frequency stabilization from Power-up (cold start)
ALL CLOCK OUTPUTS
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
T
amb
= 0
°
C to +70
°
C
MIN
1.0
1.0
UNIT
NOTES
MAX
8.0
8.0
T
PZL
, T
PZH
T
PLZ
, T
PHZ
Output enable time
Output disable time
ns
ns
NOTES:
1. See Figure 3 for measure points.
2. Period, jitter, offset, and skew are measured on the rising edge @ 1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks.
3. The PCICLK is the CPUCLK divided by two at CPUCLK = 66.6MHz. PCICLK is the CPUCLK divided by three at CPUCLK = 100MHz.
4. The CPUCLK must always lead the PCICLK as shown in Figure 2.
5. T
HKH
is measured @ 2.0V as shown in Figure 4.
6. T
HKL
is measured @ 0.4V as shown in Figure 4.
7. The time is specified from when V
DDQ
achieves its nominal operating level (typical condition is V
DDQ
= 3.3V) until the frequency output is
stable and operating within specification.
8. Defined as once the clock is at its nominal operating frequency, the adjacent period changes cannot exceed the time specified.
9. T
HRISE
and T
HFALL
are measured as a transition through the threshold region V
OL
= 0.4V and V
OH
= 2.0V (1mA) JEDEC specification.
10.T
HRISE
and T
HFALL
(48MHz, REF, PC) are measured as a transition through the threshold region V
OL
= 0.4V and V
OH
= 2.4V
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