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參數(shù)資料
| 型號(hào)： | PCK2000 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | CK97 (66/100MHz) System Clock Generator(CK97 (66/100MHz) 系統(tǒng)時(shí)鐘發(fā)生器) |
| 中文描述： | CK97（66/100MHz）系統(tǒng)時(shí)鐘發(fā)生器（CK97（66/100MHz）系統(tǒng)時(shí)鐘發(fā)生器） |
| 文件頁(yè)數(shù)： | 5/14頁(yè) |
| 文件大?。?/td> | 90K |
| 代理商： | PCK2000 |
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Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
1998 Sep 29
5
FUNCTION TABLE
SEL 100/66
CPU/PCI RATIO
CPUCLK (0–3)
(MHz)
CPICLK (1–7)
PCICLK_F
(MHz)
REF (0–2)
IOAPIC (0–1)
(MHz)
48MHz (0–1)
0
2
66.66
33.33
14.318
48
1
3
100
33.33
14.318
48
CLOCK ENABLE CONFIGURATION
CPUSTOP
PCISTOP
PWRDWN
CPUCLK
PCICLK
PCICLK_F
OTHER
CLOCKS
PLLs
OSCILLATOR
X
X
0
LOW
LOW
LOW
Stopped
OFF
OFF
0
0
1
LOW
LOW
33MHz
Running
Running
Running
0
1
1
LOW
33MHz
33MHz
Running
Running
Running
1
0
1
100/66MHz
LOW
33MHz
Running
Running
Running
1
1
1
100/66MHz
33MHz
33MHz
Running
Running
Running
POWER MANAGEMENT REQUIREMENTS
LATENCY
SIGNAL
SIGNAL STATE
NO. OF RISING EDGES OF FREE RUNNING
PCICLK
CPUSTOP
0 (DISABLED)
1
1 (ENABLED)
1
PCISTOP
0 (DISABLED)
1
1 (ENABLED)
1
PWRDWN
1 (NORMAL OPERATION)
3ms
0 (POWER DOWN)
2 MAX
NOTES:
1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the
first valid clock that comes out of the device.
2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCK2000DL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CK97 66/100MHz System Clock Generator |
| PCK2000DL-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| PCK2000M | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CK97 66/100MHz Mobile System Clock Generator |
| PCK2000MDB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CK97 66/100MHz Mobile System Clock Generator |
| PCK2000MDB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
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