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參數(shù)資料
| 型號(hào)： | PCICLOCKGEN_R001 |
| 英文描述： | AMD Alchemy? Solutions Au1500? PCI Clock Generation? |
| 中文描述： | 采用AMD Alchemy？解決方案Au1500？ PCI時(shí)鐘產(chǎn)生？ |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大小： | 25K |
| 代理商： | PCICLOCKGEN_R001 |
Application Note
3
PCI Clock Generation on the Au1500 Processor
Rev. 001
April 2002
Overview
The Au1500 processor provides the capability to internally generate a PCI clock. This, however,
may not be appropriate in all situations. The method and limitations inherent in generating an internal
PCI clock is discussed in this document.
For those systems where internal generation of the PCI clock is insufficient, the Au1500 processor
also provides the capability to use an externally generated PCI clock.
External Connections
For internal PCI clock generation the PCICLKO pin is used to generate the PCI clock. The generated
clock must also be fed back into the PCICLK pin to drive the PCI interface logic. If an externally
generated clock must be used, the clock only needs to be driven into the PCICLK pin. The PCICLKO
pin is left unconnected when an externally generated clock is being used.
Limitations on Internal PCI Clock Generation
The internal frequency generation circuitry of the Au1500 processor is fairly flexible, but there are
some limitations on the frequencies that can be generated. Either the CPU PLL or the AUX PLL may
be used as the root source of the PCI clock generator. The AUX PLL has the advantage that it is
independent of CPU frequency. However, the system designer must take into account that the AUX
PLL is also used to generate the USB clocks, which are required to be 48 MHz.
All of the frequencies in the system are generated from the 12-MHz oscillator. The AUX PLL
multiplies this up to some base frequency, from which the target frequency may be divided. The
dividers can be programmed to divide only by even values so this places further constraints on the
available frequencies.
If the AUX PLL is going to be used to generate both the USB clock and the PCI clock, it should be
programmed to 384 MHz by setting the
sys_auxpll
register to 32. This allows generation of the 48-
MHz USB clock by setting the frequency generator to divide by 8. Setting a frequency generator to
divide by 6 can generate a 64-MHz PCI clock, or dividing by 12 can generate a 32-MHz clock.
If the AUX PLL is not going to be used for USB clock generation, it can be set to 396 MHz and yield
66 MHz and 33 MHz with the same dividers. Alternately, if the CPU is being run at 396 MHz, the
CPU PLL can be used as the root clock to frequency generator 3 with the same effect.
Programming Example
The CPU PLL and AUX PLL frequencies are set by writing to the
sys_cpupll
(0xB1900060) and
sys_auxpll
(0xB1900064) registers. The value written is multiplied by 12 to yield the resulting PLL
frequency. For an AUX PLL frequency of 384 MHz, write 0x21 to location 0xB1900064.
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