參數(shù)資料
型號(hào)： PCI9060
廠商： Electronic Theatre Controls, Inc.
英文描述： 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
中文描述： 12O兼容的PCI總線(xiàn)主控接口芯片的適配器和嵌入式系統(tǒng)
文件頁(yè)數(shù)： 12/192頁(yè)
文件大?。?/td> 1551K
代理商： PCI9060
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SECTION 1
PCI 9080
GENERAL DESCRIPTION
PLX Technology, Inc., 1997
Page 3
Version 1.02
1.2 MAJOR FEATURES
PCI 2.1 Compliant.
PCI 9080 is compliant with all
aspects of PCI specification v2.1.
I
2
O Messaging Unit.
PCI 9080 incorporates an I
2
O
messaging unit. This enables the adapter or embedded
system to communicate with other I
2
O-supported
devices. I
2
O messaging unit is fully compatible with the
PCI extension of the I
2
O specification v1.5.
Dual Independent Programmable DMA Controllers
with Programmable FIFOs.
PCI 9080 provides two
independently programmable DMA controllers with
programmable FIFOs for each channel. Each channel
supports nonchaining and chaining DMA modes,
demand mode DMA, and End of Transfer (EOT) mode.
Direct Bus Master.
PCI 9080 supports memory-mapped
bursts, transfer accesses, and I/O-mapped single-
transfer accesses to the PCI bus from the Local Bus
Master. PCI 9080 also supports PCI bus interlock
(LOCK#) cycles. Read and write FIFOs enable high-
performance bursting.
PCI Host Capability.
In direct master mode, PCI 9080
can generate Type 0 or Type 1 PCI configuration cycles.
Direct Slave.
PCI 9080 supports burst memory mapped
and single I/O-mapped accesses to the local bus. Read
and write FIFOs enable high-performance bursting.
Programmable Local Bus Modes.
PCI 9080 is a PCI
bus master interface chip that connects a PCI bus to one
of three local bus types, selected through mode pins.
PCI 9080 may be connected to any local bus with a
similar design with little or no glue logic. Table 1-1 lists
the three modes.
Table 1-1. Programmable Local Bus Modes
Mode
Description
C
32-bit address/32-bit data, nonmultiplexed
J
32-bit address/32-bit data, multiplexed
S
32-bit address/16-bit data, multiplexed
Interrupt Generator.
PCI 9080 can generate PCI and
local interrupts from several sources.
Clock.
PCI 9080 local bus interface runs from a local
TTL clock and generates the necessary internal clocks.
This clock runs asynchronously to the PCI clock. There
is a buffered PCI clock (BPCLKo) for the local side to
use. BPCLKo may be connected to LCLK.
3.3 Volt and 5 Volt Operation.
PCI 9080 core requires
5 V VCC. PCI 9080 provides 3.3 or 5 volt signaling on
the PCI bus. The local bus operates at a 5V signaling
level.
Serial EEPROM Interface.
PCI 9080 contains an
optional serial EEPROM interface that can be used to
load configuration information. This is useful for loading
information that is unique to a particular adapter (such
as Network ID or Vendor ID).
Mailbox Registers.
PCI 9080 contains eight 32 bit
mailbox registers that may be accessed from the PCI or
local bus.
Doorbell Registers.
PCI 9080 includes two 32 bit
doorbell registers. One generates interrupts from the PCI
bus to local bus. The other generates interrupts from the
local bus to the PCI bus.
Unaligned DMA Transfer Support.
PCI 9080 can
transfer data on any byte boundary.
Big/Little Endian Conversion.
PCI 9080 supports
dynamic switching between Big Endian and Little Endian
operations for Direct Slave, Direct Master, DMA, and the
internal register accesses on the local side.
PCI 9080 supports on-the-fly Endian conversion for
Space 0, Space 1, and expansion ROM space. The local
bus can be Big/Little Endian by using the BIGEND# input
pin or programmable internal register configuration.
When BIGEND# is asserted, it overwrites the internal
register configuration.
Note:
PCI bus is always Little Endian.
Read Ahead Mode.
PCI 9080 supports read ahead
mode, where prefetched data can be read from the PCI
9080 internal FIFO instead of the local side. Address
must be subsequent to previous address and 32-bit
aligned (next address = current address + 4).
Programmable Bus Wait States.
PCI 9080 can be
programmed to keep the PCI bus by generating a wait
state(s), de-asserting TRDY#, if write FIFO becomes full.
PCI 9080 can also be programmed to keep the local
bus. LHOLD is asserted, if Direct Slave Write FIFO
becomes empty or Direct Slave Read FIFO becomes
full. The local bus is dropped in either case when Local
Bus Latency Timer is enabled and expires.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCI90603A 制造商:PLX Technology 功能描述:
PCI9060-3A 制造商:PLX Technology 功能描述:
PCI9060-3AF 功能描述:數(shù)字總線(xiàn)開(kāi)關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開(kāi)關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel
PCI9060ES 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
PCI9060ESF 功能描述:數(shù)字總線(xiàn)開(kāi)關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開(kāi)關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel
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