參數(shù)資料
型號(hào): PCI-WDT
英文描述: UEBERWACHUNGSKARTE PLUG AND PLAY
中文描述: UEBERWACHUNGSKARTE即插即用
文件頁(yè)數(shù): 19/31頁(yè)
文件大?。?/td> 334K
代理商: PCI-WDT
Chapter 3
Programming Details
Page 9
Blue Chip Technology Ltd.
01270202.doc
Page 9
Watchdog Timer
The watchdog timer comprises of an 8-bit load counter with a time base of 2 Hz
giving a watchdog refresh period of 1 to 255 seconds. The watchdog refresh
period is set through register Base2 + 8h. The watchdog timer can be enabled/
disabled through bit 0 of register Base2 + 9h.
Isolated External Input
The status of the external input can be read directly from port Base2 + 9 bit 4.
In addition a change of state on this input can generate a interrupt to the system.
This interrupt operation can enabled/disabled through port Base2+ 9 bit 1.
Interrupt Selection
A total of 10 sources of interrupt are available from the supply, fans,
temperature, external input and watchdog timer monitors. These interrupts are
divided between the LM78 functions ( power fan and temperature monitors) and
the non LM78 functions ( watchdog timer and External input).
The LM78 can generate interrupts on the occurrence of an out of limit condition
on one of more of the enabled LM78 monitor circuits. The LM78 produces a
single interrupt signal which is in turn combined on board with the non-LM78
monitor circuits to produce a single interrupt signal for the PCI-WD. The
interrupt status registers are located at LM78 register addresses 41h and 42H. A
full description of these registers and their bit assignments can be found in the
appendices.
The non-LM78 function interrupts are accessed at Base2 + 9. The bit
assignments for these interrupts can be found in the previous section. Given the
combined gating of the various interrupt sources, the source of the interrupt
must first be determined by reading the Interrupt status register at address
Base3 + 1h. This determines if the interrupt was generated by the LM78, the
watchdog timer or the external input. If it was the LM78 its Interrupt registers
must then be read. Having serviced an interrupt, the source should be cleared by
momentarily clearing the relevant bit in the interrupt enable register ( Base 2 +
9).
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