參數(shù)資料
型號: PCF88332DA
廠商: NXP Semiconductors N.V.
英文描述: STN RGB - 132 X 132 X 3 driver
中文描述: 超扭曲的RGB - 132 × 132 × 3驅(qū)動程序
文件頁數(shù): 78/112頁
文件大?。?/td> 469K
代理商: PCF88332DA
2003 Feb 14
78
Philips Semiconductors
Objective specification
STN RGB - 132
×
132
×
3 driver
PCF8833
Notes
1.
2.
3.
V
DD2
and V
DD3
always have to be larger than or equal to V
DD1
.
Not directly observable at any pin.
After calibration the following f
osc
can be expected at 25
°
C: 600 kHz
±
4%; at different temperatures an additional
variation of +0.12%/
°
C will not be exceeded.
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
V
IL
and V
IH
with an input voltage swing of V
SS1
to V
DD1
.
The initialization incorporates the start-up of the internal circuitry including the readout of the OTP cells. The start-up
time for the internal voltage generation is not included.
The input signal rise time and fall time (t
r
and t
f
) are specified at 15 ns or less. When the cycle time is used at high
speed, the specification is t
r
+ t
f
(t
CYC
t
CCLW
t
CCHW
) or t
r
+ t
f
(t
CYC
– t
CCLR
t
CCHR
).
CS can be permanently tied LOW.
The output disable time and read access time is applicable after the second read cycle (see Fig.40).
For V
DD1
= 1.8 V possible variation of t
OH
is between 40 and 80 ns for a temperature range of
40 to +85
°
C.
4.
5.
6.
7.
8.
9.
handbook, full pagewidth
VDD1
MGU966
VIL
VIH
VIL
VIH
VDD1
RES
RES
Status
resetting
normal operation
Status
resetting
normal operation
Interface:
commands/data
not accepted
accepted
not accepted
accepted
tRI
tRI
tRSS
tSU;RESL
tW(RESL)
tRT
tW(RESL)
tW(RESL)
tRT
Fig.50 Reset timing.
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