參數(shù)資料
型號(hào)： PCF88332DA
廠商： NXP Semiconductors N.V.
英文描述： STN RGB - 132 X 132 X 3 driver
中文描述： 超扭曲的RGB - 132 × 132 × 3驅(qū)動(dòng)程序
文件頁(yè)數(shù)： 50/112頁(yè)
文件大?。?/td> 469K
代理商： PCF88332DA
2003 Feb 14
50
Philips Semiconductors
Objective specification
STN RGB - 132
×
132
×
3 driver
PCF8833
6.2.34
S
UPER FRAME INVERSION
The Super frame inversion command (FINV), which is the inversion of the row functions after all rows are written to can
be switched off for the PCF8833. When switched off, the inversion of the row functions will then only be done with N-line
inversion. Inversion of the row functions is needed so as to avoid a DC component over the LCD display. A detailed
description of the N-line inversion is given in Section 6.2.45.
The FINV control bit reset state is defined in Table 52.
Table 52
Super frame inversion register bits
Table 53
Super frame inversion reset state
6.2.35
D
ATA ORDER
The data order (DOR) of the data which will be written into the RAM can be changed (swapped).
The DOR command is explained and the reset state defined in Table 55.
Table 54
Data order register bits
Table 55
Data order reset state
6.2.36
T
EMPERATURE COMPENSATED FRAME FREQUENCY
The PCF8833 incorporates a temperature segmented frame frequency programming; see Section 6.2.41. This
segmented frame frequency can be disabled by using the temperature compensated frame frequency (TCDFE)
command.
The TCDFE control bit reset state is defined in Table 57.
When the non-segmented frame frequency is chosen, the frame frequency in segment B (DFB) is valid;
see Section 6.2.41.
Table 56
Temperature compensated frame frequency register bits
D/C
7
6
5
4
3
2
1
0
DEFAULT
0
1
0
1
1
1
0
0
FINV
B9H
BIT
LOGIC 0
LOGIC 1 (RESET STATE)
FINV
super frame inversion is off
super frame inversion is on
D/C
7
6
5
4
3
2
1
0
DEFAULT
0
1
0
1
1
1
0
1
DOR
BAH
BIT
LOGIC 0 (RESET STATE)
LOGIC 1
DOR
normal data order
MSB/LSB transposed for RAM data
D/C
7
6
5
4
3
2
1
0
DEFAULT
0
1
0
1
1
1
1
0
TCDFE
BDH
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