參數(shù)資料
型號： PCF88331
廠商： NXP Semiconductors N.V.
英文描述： STN RGB - 132 X 132 X 3 driver
中文描述： 超扭曲的RGB - 132 × 132 × 3驅(qū)動程序
文件頁數(shù)： 63/112頁
文件大?。?/td> 469K
代理商： PCF88331
2003 Feb 14
63
Philips Semiconductors
Objective specification
STN RGB - 132
×
132
×
3 driver
PCF8833
7.2.2
R
AM ACCESS ARBITER
The function of the arbiter is to handle the data flow. If a
write access is done on the RAM and a read access is
requested at the same time, then the arbiter will ensure
that there are no data collisions. Writing data to the RAM
has priority. Therefore no handshaking is done at the
interface side and the data can be applied to the interface
without having data read/write errors on the RAM.
7.2.3
WR
ADDRESS COUNTER
The address counter sets the addresses of the display
data RAM for writing.
Data is written pixel wise into the RAM of the PCF8833.
Thedataforonepixeliscollected(RGB4 : 4 : 4 bit)before
it is written into the display data RAM. The RAM locations
are addressed by the address pointers. The address
ranges are X = 0 to X = 131 (83H) and Y = 0 to
Y = 131 (83H). Addresses outside of these ranges are not
allowed.
Before writing to the RAM a window must be defined into
which data will be written. The window is programmable
via the command registers xs and ys (designating the start
address) and xe and ye (designating the end address).
For example, if the whole display content is written, the
windowwillbedefinedbythefollowingvalues:xs = 0 (0H),
ys = 0 (0H), xe = 131 (83H) and ys = 131 (83H).
In the vertical addressing mode (V = 1), the Y address
increments after each pixel. After the last Y address
(Y = ye), Y wraps around to ys and X increments to
address the next column. In horizontal addressing mode
(V = 0), the X address increments after each pixel. After
the last X address (X = xe), X wraps around to xs and
Y increments to address the next row. After the very last
address (X = xe and Y = ye) the address pointers wrap
around to address (X = xs and Y = ys).
For flexibility in handling a wide variety of display
architectures, the command ‘Memory Data Access
Control (MADCTL)’ (see Section 6.2.27) defines flags
MX and MY, which allows mirroring of the X and
Y addresses. All combinations of flags are allowed.
Figures 34, 35 and 36 show the possible combinations of
writing to the display RAM. When MX, MY and V is
changed, the data must be re-written to the display RAM.
7.2.4
D
ISPLAY ADDRESS COUNTER
The display address counter generates the addresses for
readout of the display data RAM.
handbook, halfpage
MGU943
ys
ye
xe
xs
131
0
X address
131
Y
handbook, halfpage
MGU944
ys
ye
xe
xs
131
0
X address
131
Y
Fig.34 Sequence of writing data bytes into RAM showing function of V bit.
V = 0; MX = 0 and MY = 0.
V = 1; MX = 0 and MY = 0.
相關(guān)PDF資料
PDF描述
PCF88332DA STN RGB - 132 X 132 X 3 driver
PCF8833U STN RGB - 132 X 132 X 3 driver
PCF8881 132 x 132 RGB single chip TFT driver with DC-to-DC converter
PCI-ADC MULTIFUNKTIONSKARTE 44 KANAL PCI BUS
PCI-DIO KARTE E/A 32 KANAL PCI BUS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCF88332DA 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:STN RGB - 132 X 132 X 3 driver
PCF8833U 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:STN RGB - 132 X 132 X 3 driver
PCF8833U/2DA 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:STN RGB - 132 X 132 X 3 driver
PCF8881 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:132 x 132 RGB single chip TFT driver with DC-to-DC converter
PCF8881U/2DA 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:132 x 132 RGB single chip TFT driver with DC-to-DC converter
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