
2004 Mar 05
7
Philips Semiconductors
Product specification
(67 + 1)
×
102 pixels matrix LCD driver
PCF8813
7
FUNCTIONAL DESCRIPTION
7.1
I/O buffer and interface
One of five industrial standard interfaces can be selected
using the interface configuration inputs PS2, PS1 and
PS0.
Table 1
Parallel/serial/I
2
C-bus interface selection
7.2
Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required.
An external clock signal, if used, is connected to this input.
7.3
Address counter
The Address Counter (AC) assigns addresses to the
displaydata RAMforwriting. The X address X[6:0] andthe
Y address Y[3:0] are set separately.
7.4
Display data RAM
The PCF8813 contains a 68
×
102 bit static RAM which
stores the display data. The Display Data RAM (DDRAM)
is divided into eight banks of 102 bytes (8
×
8
×
102 bits),
one bank of 1
×
3
×
102 bits and a separate bank of
1
×
1
×
102 for icons. During RAM access, data is
transferredtotheRAMviaanyofthefour interfaces.There
is a direct correspondence between the X address and the
column output number.
7.5
Timing generator
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not affected by operations on the data buses.
7.6
Display address counter
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The display status (all dots on/off and normal/inverse
video) is set by bits D and E in the display control
command.
7.7
LCD row and column drivers
The PCF8813 contains 68 row and 102 column drivers,
which connect the appropriate LCD bias voltages in a
sequence to the display in accordance with the data that is
to be displayed. Figure 2 shows typical waveforms.
Unused outputs should be left unconnected.
PS2
PS1
PS0
INTERFACE
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
3-line SPI
4-line SPI
8080 parallel interface
6800 parallel interface
high-speed I
2
C-bus interface
3-line serial interface