參數(shù)資料
型號(hào): PCF8812
廠商: NXP Semiconductors N.V.
英文描述: CRYSTAL, 8.0 MHZ
中文描述: 65 × 102像素矩陣LCD驅(qū)動(dòng)器
文件頁數(shù): 21/36頁
文件大?。?/td> 201K
代理商: PCF8812
2000 Nov 22
21
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
PCF8812
Notes
1.
2.
3.
4.
5.
6.
The maximum possible V
LCD
voltage that may be generated is dependent on voltage, temperature and (display) load.
Internal clock.
f
SCLK
= 0 means no serial clock.
During power-down all static currents are switched off.
If external V
LCD
; the display load current is not transmitted to I
DD
.
Tolerance depend on the temperature; (typical null at T
amb
= 27
°
C, maximum tolerance values are measured at the
temperate range limit, maximum tolerance is proportional to V
LCD
).
For TC1 to TC3.
7.
14 AC CHARACTERISTICS
V
DD
= 2.5 to 5.5 V; V
SS
= 0 V; V
LCD
= 4.5 to 9.0 V; T
amb
=
40 to +85
°
C; unless otherwise specified.
LCD supply voltage generator
V
LCD
V
LCD
tolerance internally
generated
V
DD1
= 2.8 V; V
LCD
= 7.6 V;
f
SCLK
= 0; T
amb
= 25
°
C;
display-load = 10
μ
A;
notes 3, 6 and 7
300
0
+300
mV
TC
V
LCD
temperature coefficient V
DD1
= 2.8 V; f
SCLK
= 0;
T
amb
=
20 to +70
°
C;
display load = 10
μ
A; note 3
coefficient 0
coefficient 1
coefficient 2
coefficient 3
0
×
10
3
0.76
×
10
3
1.05
×
10
3
2.10
×
10
3
1/
°
C
1/
°
C
1/
°
C
1/
°
C
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
f
OSC
oscillator frequency
V
DD1
= 2.8 V;
T
amb
=
20 to +70
°
C
22
38
67
kHz
f
clk(ext)
f
frame
external clock frequency
frame frequency
20
38
73
67
kHz
Hz
f
OSC
or f
clk(ext)
= 38 kHz;
note 1
see Fig.16
see Fig.16
t
VHRL
t
RW
Serial bus timing characteristics
V
DD
to RES LOW
RES LOW pulse width
0
500
1
μ
s
ns
f
SCLK
clock frequency
V
DD1
= 3.0 V
±
10%; all
signal timing is based on
20% to 80% of V
DD
and a
maximum rise and fall time
of 10 ns
0
4.00
MHz
t
cyc
t
PWH1
t
PWL1
t
S2
clock cycle time
SCLK pulse width HIGH
SCLK pulse width LOW
SCE set-up time
250
100
100
60
ns
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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