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參數(shù)資料
| 型號： | PCF8812 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | CRYSTAL, 8.0 MHZ |
| 中文描述： | 65 × 102像素矩陣LCD驅(qū)動器 |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 201K |
| 代理商： | PCF8812 |
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2000 Nov 22
10
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
PCF8812
handbook, full pagewidth
MGS396
0
1
2
102
103
104
204
205
206
306
307
308
408
409
410
510
511
512
612
613
614
714
715
716
816
817
818
0
8
917
0
101
X address
Y address
Fig.6 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).
10 INSTRUCTIONS
The instruction format is divided into two modes: If D/C
(mode select) is set LOW the current byte is interpreted as
command byte (see Table 1). Figure 8 shows an example
of a serial data stream for initializing the chip. If D/C is set
HIGH the following bytes are stored in the display data
RAM. After every data byte the address counter is
incremented automatically. The level of the D/C signal is
read during the last bit of the data byte. Every instruction
can be sent in any order to the PCF8812. The MSB of a
byte is transmitted first. Figure 8 shows one possible
command stream, used to set-up the LCD driver. The
serial interface is initialized when SCE is HIGH. In this
state SCLK clock pulses have no effect and no power is
consumed by the serial interface. A negative edge on SCE
enablestheserialinterfaceandindicatesthestartofadata
transmission.
Figures 9 and 10 show the serial bus protocol:
When SCE is HIGH, SCLK clocks are ignored. During
the HIGH time of SCE the serial interface is initialized
(see Fig.12)
SDIN is sampled at the positive edge of SCLK
D/C indicates whether the byte is a command (D/C = 0)
or RAM data (D/C = 1). It is read with the eighth SCLK
pulse
If SCE stays LOW after the last bit of a command/data
byte, the serial interface expects DB7 of the next byte at
the next positive edge of SCLK (see Fig.12). If SCLK
goes LOW after the last data bit (DB0), either:
– A rising clock edge is required to latch the last data bit
– Or the last bit is latched when SCE goes HIGH.
A reset pulse with RES interrupts the transmission.
No data is written into the RAM. The registers are
cleared. If SCE is LOW after the positive edge of RES,
the serial interface is ready to receive bit 7 of a
command/data byte (see Fig.12).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCF8812U | CRYSTAL, 8,0 MHZ |
| PCF8813 | (67 + 1) x 102 pixels matrix LCD driver |
| PCF88132 | (67 + 1) x 102 pixels matrix LCD driver |
| PCF88132DA | (67 + 1) x 102 pixels matrix LCD driver |
| PCF8813U | (67 + 1) x 102 pixels matrix LCD driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCF8812U | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:65 x 102 pixels matrix LCD driver |
| PCF8812U/2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:65 x 102 pixels matrix LCD driver |
| PCF8812U/2/F1 | 制造商:PH 功能描述: |
| PCF8813 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:(67 + 1) x 102 pixels matrix LCD driver |
| PCF88132 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:(67 + 1) x 102 pixels matrix LCD driver |
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