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參數(shù)資料
| 型號： | PCF8579U7 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | LCD column driver for dot matrix graphic displays |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC55 |
| 封裝： | DIE-56 |
| 文件頁數(shù)： | 8/40頁 |
| 文件大?。?/td> | 287K |
| 代理商： | PCF8579U7 |
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1997 Apr 01
8
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
7
FUNCTIONAL DESCRIPTION
The PCF8579 column driver is designed for use with the
PCF8578. Together they form a general purpose LCD dot
matrix chip set.
Typically up to 16 PCF8579s may be used with one
PCF8578. Each of the PCF8579s is identified by a unique
4-bit hardware subaddress, set by pins A0 to A3.
The PCF8578 can operate with up to 32 PCF8579s when
using two I
2
C-bus slave addresses. The two slave
addresses are set by the logic level on input SA0.
7.1
Multiplexed LCD bias generation
The bias levels required to produce maximum contrast
depend on the multiplex rate and the LCD threshold
voltage (V
th
). V
th
is typically defined as the RMS voltage at
which the LCD exhibits 10% contrast. Table 1 shows the
optimum voltage bias levels for the PCF8578/PCF8579
chip set as functions of V
op
(V
op
= V
DD
V
LCD
), together
with the discrimination ratios (D) for the different multiplex
rates. A practical value for V
op
is obtained by equating
V
off(rms)
with V
th
. Figure 4 shows the first 4 rows of Table 1
as graphs.
Table 1
Optimum LCD bias voltages
PARAMETER
MULTIPLEX RATE
1 : 8
1 : 16
1 : 24
1 : 32
0.739
0.800
0.830
0.850
0.522
0.600
0.661
0.700
0.478
0.400
0.339
0.300
0.261
0.200
0.170
0.150
0.297
0.245
0.214
0.193
0.430
0.316
0.263
0.230
1.447
1.291
1.230
1.196
3.370
4.080
4.680
5.190
V
2
op
V
V
3
V
op
--------
V
4
op
V
V
5
V
op
--------
V
V
op
)
-----------------------
V
op
)
-----V
D
V
V
off rms
)
)
-----------------------
=
V
th
V
7.2
Power-on reset
At power-on the PCF8579 resets to a defined starting
condition as follows:
1.
Display blank (in conjunction with PCF8578)
2.
1 : 32 multiplex rate
3.
Start bank, 0 selected
4.
Data pointer is set to X, Y address 0, 0
5.
Character mode
6.
Subaddress counter is set to 0
7.
I
2
C-bus is initialized.
Data transfers on the I
2
C-bus should be avoided for 1 ms
following power-on, to allow completion of the reset action.
Fig.4
V
bias
/V
op
as a function of the multiplex rate.
1:8
1:16
1:32
1.0
0
0.8
MSA838
1:24
multiplex rate
0.6
0.4
0.2
Vbias
Vop
V5
V4
V3
V2
V
bias
= V
2
, V
3
, V
4
, V
5
. See Table 1.
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