參數(shù)資料
型號(hào)： PCF8579U7
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 顯示驅(qū)動(dòng)器
英文描述： LCD column driver for dot matrix graphic displays
中文描述： LIQUID CRYSTAL DISPLAY DRIVER, UUC55
封裝： DIE-56
文件頁(yè)數(shù)： 21/40頁(yè)
文件大?。?/td> 287K
代理商： PCF8579U7
1997 Apr 01
21
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
9
CHARACTERISTICS OF THE I
2
C-BUS
The I
2
C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL) which
must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
9.1
Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this moment will be interpreted as control signals.
9.2
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH, is defined as the start condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH, is defined as the stop condition (P).
9.3
System configuration
A device transmitting a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message flow is the ‘master’ and the devices
which are controlled by the master are the ‘slaves’.
9.4
Acknowledge
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is
unlimited. Each data byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter, whereas the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges must pull down
the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal the end of a data transmission to the transmitter by
not
generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a stop condition.
Fig.13 Bit transfer.
MBA607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
相關(guān)PDF資料
PDF描述
PCF8579H LCD column driver for dot matrix graphic displays
PCF8582C-2 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface
PCF85XXC-2 2 POLE 480VAC 30A AC CONTROL
PCF8594C-2 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface
PCF8594C-2P PCF85xxC-2 family 256 to 1024 ⅴ 8-bit CMOS EEPROMs with I2C-bus interface
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCF8582C 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Smart, simple solutions for the 12 most common design concerns
PCF8582C-2 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:256 x 8-bit CMOS EEPROMS with I2C-bus interface
PCF8582C-2_04 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:256 x 8-bit CMOS EEPROM with I2C-bus interface
PCF8582C2D 制造商:NXP Semiconductors 功能描述: 制造商:NXP Semiconductors 功能描述:EEPROM Serial-I2C 2K-Bit 256 x 8 3.3V/5V 8-Pin SO Tube
PCF8582C2N 功能描述:電可擦除可編程只讀存儲(chǔ)器 電可擦除可編程只讀存儲(chǔ)器 256X8 W/I2C 100KHZ -40+85 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*