參數(shù)資料
型號(hào): PCF8576C
廠商: NXP Semiconductors N.V.
英文描述: Universal LCD driver for low multiplex rates
中文描述: 通用LCD驅(qū)動(dòng)器的低復(fù)用率
文件頁(yè)數(shù): 24/40頁(yè)
文件大?。?/td> 243K
代理商: PCF8576C
1998 Feb 06
24
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
Table 13
BANK SELECT option 2
Table 14
BLINK option 1
Table 15
BLINK option 2
7.9
Display controller
The display controller executes the commands identified
by the command decoder. It contains the status registers
of the PCF8576 and co-ordinates their effects.
The controller is also responsible for loading display data
into the display RAM as required by the filling order.
STATIC
1 : 2 MUX
BIT O
RAM bit 0
RAM bit 2
RAM bits 0 and 1
RAM bits 2 and 3
0
1
BLINK FREQUENCY
BITS
BF1
BF0
Off
2 Hz
1 Hz
0.5 Hz
0
0
1
1
0
1
0
1
BLINK MODE
BIT A
Normal blinking
Alternation blinking
0
1
7.10
Cascaded operation
In large display configurations, up to 16 PCF8576s can be
distinguished on the same I
2
C-bus by using the 3-bit
hardware subaddress (A0, A1 and A2) and the
programmable I
2
C-bus slave address (SA0). When
cascaded PCF8576s are synchronized so that they can
share the backplane signals from one of the devices in the
cascade. Such an arrangement is cost-effective in large
LCD applications since the backplane outputs of only one
device need to be through-plated to the backplane
electrodes of the display. The other PCF8576s of the
cascade contribute additional segment outputs but their
backplane outputs are left open-circuit (see Fig.18).
The SYNC line is provided to maintain the correct
synchronization between all cascaded PCF8576s.
This synchronization is guaranteed after the Power-on
reset. The only time that SYNC is likely to be needed is if
synchronization is accidentally lost (e.g. by noise in
adverse electrical environments; or by the definition of a
multiplex mode when PCF8576s with differing SA0 levels
are cascaded). SYNC is organized as an input/output pin;
the output selection being realized as an open-drain driver
with an internal pull-up resistor. A PCF8576 asserts the
SYNC line at the onset of its last active backplane signal
and monitors the SYNC line at all other times. Should
synchronization in the cascade be lost, it will be restored
by the first PCF8576 to assert SYNC. The timing
relationship between the backplane waveforms and the
SYNC signal for the various drive modes of the PCF8576
are shown in Fig.19.
For single plane wiring of packaged PCF8576s and
chip-on-glass cascading, see Chapter 12.
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