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參數(shù)資料
| 型號： | PCF8573P |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | Clock/calendar with Power Fail Detector |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, SOT-38-4, DIP-16 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 198K |
| 代理商： | PCF8573P |
1997 Mar 28
6
Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
PCF8573
7.5
Power on/power fail detection
If the voltage V
DD
V
SS1
falls below a certain value the
operation of the clock becomes undefined. Thus a warning
signal is required to indicate that faultless operation of the
clock is not guaranteed. This information is latched in a
flag called POWF (Power Fail) and remains latched after
restoration of the correct supply voltage until a write
procedure with EXECUTE ADDRESS has been received.
The flag POWF can be set by an internally generated
power fail level-discriminator signal for application with
(V
DD
V
SS1
) greater than V
TH1
, or by an externally
generated power fail signal for application with
(V
DD
V
SS1
) less than V
TH1
. The external signal must be
applied to the input PFIN. The input stage operates with
signals of slow rise and fall times. Internally or externally
controlled POWF can be selected by input EXTPF as
shown in Table 2.
Table 2
Power fail selection
Note
1.
0 = V
SS1
(LOW); 1 = V
DD
(HIGH).
EXTPF
(1)
PFIN
(1)
FUNCTION
0
0
1
1
0
1
0
1
power fail is sensed internally
test mode
power fail is sensed externally
no power fail sensed
The external power fail control operates by absence of the
V
DD
V
SS2
supply. Therefore the input levels applied to
PFIN and EXTPF must be within the range of V
DD
V
SS1
.
A LOW level at PFIN indicates a power fail. POWF is
readable via the I
2
C-bus. A power-on reset for the I
2
C-bus
control is generated on-chip when the supply voltage
V
DD
V
SS2
is less than V
TH2
.
7.6
Interface level shifters
The level shifters adjust the 5 V operating voltage
(V
DD
V
SS2
) of the microcontroller to the internal supply
voltage (V
DD
V
SS1
) of the clock/calendar. The oscillator
and counter are not influenced by the V
DD
V
SS2
supply
voltage. If the voltage V
DD
V
SS2
is absent (V
DD
= V
SS2
)
the output signal of the level shifter is HIGH because V
DD
is the common node of the V
DD
V
SS2
and the V
DD
V
SS1
supplies. Because the level shifters invert the input
signals, the internal circuit behaves as if a LOW signal is
present on the inputs. FSET, SEC, MIN and COMP are
CMOS push-pull output stages. The driving capability of
these outputs is lost when the supply voltage
V
DD
V
SS2
= 0.
相關PDF資料 |
PDF描述 |
|---|---|
| PCF8573T | Clock/calendar with Power Fail Detector |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PCF8573PN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
| PCF8573T | 制造商: 功能描述: 制造商:undefined 功能描述: 制造商:NXP Semiconductors 功能描述:Real Time Clock, 16 Pin, Plastic, SOP |
| PCF8573TD | 制造商:NXP Semiconductors 功能描述:Real Time Clock, 16 Pin, Plastic, SOP |
| PCF8573TD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
| PCF8574 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:REMOTE 8-BIT I/O EXPANDER FOR I2C BUS |
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