參數(shù)資料
型號: PCF8573P
廠商: NXP SEMICONDUCTORS
元件分類: XO, clock
英文描述: Clock/calendar with Power Fail Detector
中文描述: 0 TIMER(S), REAL TIME CLOCK, PDIP16
封裝: 0.300 INCH, PLASTIC, SOT-38-4, DIP-16
文件頁數(shù): 16/24頁
文件大?。?/td> 198K
代理商: PCF8573P
1997 Mar 28
16
Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
PCF8573
13 AC CHARACTERISTICS
V
SS2
= 0 V; T
amb
=
40 to +85
°
C unless otherwise specified. Typical values at T
amb
= +25
°
C.
Notes
1.
All timing values are valid within the operating supply voltage and ambient temperature range and reference to V
IL
and V
IH
with an input voltage swing of V
SS
to V
DD
.
A detailed description of the I
2
C-bus specification, with applications, is given in brochure “The I
2
C-bus and how to
use it” This brochure may be ordered using the code 9398 393 40011.
2.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Rise and fall times of input signals
t
r
rise time
input EXTPF
input PFIN
all other inputs (levels
between V
IL
and V
IH
)
input EXTPF
input PFIN
all other inputs (levels
between V
IL
and V
IH
)
1
1
μ
s
μ
s
μ
s
t
f
fall time
1
0.3
μ
s
μ
s
μ
s
Oscillator
C
osc
R
f
f
osc
integrated oscillator capacitance
oscillator feedback resistance
oscillator stability
40
3
2
×
10
7
pF
M
(V
DD
V
SS1
) = 100 mV;
T
amb
= 25
°
C;
(V
DD
V
SS1
) = 1.55 V
Quartz crystal parameters (f = 32.768 kHz)
R
s
C
L
C
T
series resistance
parallel load capacitance
trimmer capacitance
5
10
40
25
k
pF
pF
I
2
C-bus timing
(see Fig.12; notes 1 and 2)
f
SCL
t
SP
t
BUF
t
SU;STA
t
HD;STA
t
LOW
t
HIGH
t
r
t
f
t
SU;DAT
t
HD;DAT
t
VD;DAT
t
SU;STO
SCL clock frequency
tolerable spike width on bus
bus free time
START condition set-up time
START condition hold time
SCL LOW time
SCL HIGH time
SCL and SDA rise time
SCL and SDA fall time
data set-up time
data hold time
SCL LOW to data out valid
STOP condition set-up time
4.7
4.7
4.0
4.7
4.0
250
0
4.0
100
100
1.0
0.3
3.4
kHz
ns
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
ns
μ
s
μ
s
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