參數(shù)資料
型號: PCF8549U
廠商: NXP Semiconductors N.V.
英文描述: 65 x 102 pixels matrix LCD driver
中文描述: 65 × 102像素矩陣LCD驅(qū)動器
文件頁數(shù): 8/36頁
文件大?。?/td> 271K
代理商: PCF8549U
1997 Nov 21
8
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
PCF8549
Addressing
The Display data RAM of the PCF8549 is accessed as
indicated in Figs 3, 4, 4, 6 and 7. The display RAM has a
matrix of 65
×
102 bits. The columns are addressed by the
address pointer. The address ranges are:
X 0 to 101 (1100101b) and Y 0 to 8 (1000b). Addresses
outside these ranges are not allowed. In vertical
addressing mode (V = 1) the Y address increments (see
Fig.7) after each byte. After the last Y address (Y = 8)
Y wraps around to 0 and X increments to address the next
column. In horizontal addressing mode (V = 0) the
X address increments (see Fig.6) after each byte. After the
last X address (X = 101) X wraps around to
0 and Y increments to address the next row. After the very
last address (X = 101 and Y = 8) the address pointers
wrap around to address (X = 0 and Y = 0).
The MX bit allows a horizontal mirroring: When MX = 1,
the X address space is mirrored: The address X = 0 is
then located at the right side (column 101) of the display
(see Fig.4). When MX = 0 the mirroring is disabled and the
address X = 0 is located at the left side (column 0) of the
display (see Fig.4).
If the RM-bit (read-modify-write mode) is set, the address
is only incremented after a write, otherwise the address is
incremented after both read and write access to the
display data RAM.
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