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參數(shù)資料
| 型號： | PCF8549U |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 65 x 102 pixels matrix LCD driver |
| 中文描述： | 65 × 102像素矩陣LCD驅(qū)動器 |
| 文件頁數(shù)： | 11/36頁 |
| 文件大?。?/td> | 271K |
| 代理商： | PCF8549U |
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1997 Nov 21
11
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
PCF8549
RAM access
If the D/C bit is 1 the RAM can be accessed in both read
and write access mode, depending on the R/W bit. The
data is written to the RAM during the acknowledge cycle.
I
2
C-BUS INTERFACE
Characteristics of the I
2
C-bus
The I
2
C-bus is for bi-directional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
B
IT TRANSFER
(see Fig.9)
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the HIGH
Fig.8 Read modify write access.
Set Address
Set Read
Modify Write Mode
Read Data
Write Data
END
Finished
no
yes
period of the clock pulse as changes in the data line at this
time will be interpreted as a control signal.
S
TART AND STOP CONDITIONS
(see Fig.10)
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is
HIGH is defined as the STOP condition (P).
S
YSTEM CONFIGURATION
(see Fig.11)
Transmitter: The device which sends the data to the bus
Receiver: The device which receives the data from the
bus
Master: The device which initiates a transfer, generates
clock signals and terminates a transfer
Slave: The device addressed by a master
Multi-Master: More than one master can attempt to
control the bus at the same time without corrupting the
message
Arbitration: Procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
Synchronisation: Procedure to synchronize the clock
signals of two or more devices.
A
CKNOWLEDGE
(see Fig.12)
Each byte of eight bits is followed by an acknowledge bit.
The acknowledge bit is a HIGH signal put on the bus by
the transmitter during which time the master generates an
extra acknowledge related clock pulse. A slave receiver
which is addressed must generate an acknowledge after
the reception of each byte. Also a master receiver must
generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The
device that acknowledges must pull-down the SDA line
during the acknowledge clock pulse, so that the SDA line
is stable LOW during the HIGH period of the acknowledge
related clock pulse (set-up and hold times must be taken
into consideration). A master receiver must signal an end
of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of
the slave. In this event the transmitter must leave the data
line HIGH to enable the master to generate a stop
condition.
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| PCF8558U | Universal LCD driver for small graphic panels |
| PCF8563 | Real-time clock/calendar(實時時鐘/日歷) |
| PCF8566 | Universal LCD driver for low multiplex rates |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PCF8549U/2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:65 x 102 pixels matrix LCD driver |
| PCF8549U/2/F1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:65 x 102 pixels matrix LCD driver |
| PCF8551ATT/AJ | 功能描述:IC LCD DRIVER UNIV 48TSSOP 制造商:nxp usa inc. 系列:- 包裝:剪切帶（CT） 零件狀態(tài):在售 顯示類型:LCD 配置:7段 + DP，14段 + DP + AP，點陣 接口:I2C 數(shù)字或字符:9 個字符，18 個字符，144 元件 電流 - 電源:1.2μA 電壓 - 電源:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商器件封裝:48-TSSOP 標準包裝:1 |
| PCF8551BTT/AJ | 功能描述:IC LCD DRIVER UNIV 48TSSOP 制造商:nxp usa inc. 系列:* 包裝:剪切帶（CT） 零件狀態(tài):在售 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商器件封裝:48-TSSOP 標準包裝:1 |
| PCF8558 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal LCD driver for small graphic panels |
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