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參數(shù)資料
| 型號： | PCF8533 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Universal LCD driver for low multiplex rates |
| 中文描述： | 通用LCD驅(qū)動器的低復用率 |
| 文件頁數(shù)： | 23/36頁 |
| 文件大小： | 158K |
| 代理商： | PCF8533 |
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1999 Jul 30
23
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
Table 9
Load data pointer option 1
Table 10
Device select option 1
Table 11
Bank select option 1 (Input)
Table 12
Bank select option 2 (Output)
Table 13
Blink option 1
Table 14
Blink option 2
Note
1.
Normal blinking is assumed when multiplex rates 1 : 3
or 1 : 4 are selected.
7.9
Display controller
The display controller executes the commands identified
by the command decoder. It contains the status registers
of the PCF8533 and co-ordinates their effects.
The controller is also responsible for loading display data
into the display RAM as required by the filling order.
7.10
Cascaded operation
In large display configurations, up to 16 PCF8533s can be
distinguished on the same I
2
C-bus by using the 3-bit
hardware subaddress (A0, A1 and A2) and the
programmable I
2
C-bus slave address (SA0). When
cascaded PCF8533s are synchronized they can share the
backplane signals from one of the devices in the cascade.
Such an arrangement is cost-effective in large LCD
applications since the backplane outputs of only one
device need to be through-plated to the backplane
electrodes of the display. The other PCF8533s of the
cascade contribute additional segment outputs but their
backplane outputs are left open-circuit (see Fig.16).
The SYNC line is provided to maintain the correct
synchronization between all cascaded PCF8533s. This
synchronization is guaranteed after the Power-on reset.
The only time that SYNC is likely to be needed is if
synchronization is accidentally lost (e.g. by noise in
adverse electrical environments, or by the definition of a
multiplex mode when PCF8533s with different SA0 levels
are cascaded). SYNC is organized as an input/output pad;
the output selection being realized as an open-drain driver
with an internal pull-up resistor. A PCF8533 asserts the
SYNC line at the onset of its last active backplane signal
and monitors the SYNC line at all other times. Should
synchronization in the cascade be lost, it will be restored
by the first PCF8533 to assert SYNC. The timing
relationship between the backplane waveforms and the
SYNC signal for the various drive modes of the PCF8533
are shown in Fig.17.
The contact resistance between the SYNC pads of
cascaded devices must be controlled. If the resistance is
too high then the device will not be able to synchronize
properly. This is particularly applicable to COG
applications. Table 15 shows the limiting values for
contact resistance.
Table 15
SYNC contact resistance
DESCRIPTION
BITS
7 bit binary value of
0 to 79
P6 P5 P4 P3 P2 P1 P0
DESCRIPTION
BITS
3 bit binary value of 0 to 7
A2
A1
A0
STATIC
1 : 2 MUX
BIT I
RAM bit 0
RAM bit 2
RAM bits 0 and 1
RAM bits 2 and 3
0
1
STATIC
1 : 2 MUX
BIT O
RAM bit 0
RAM bit 2
RAM bits 0 and 1
RAM bits 2 and 3
0
1
BLINK FREQUENCY
BITS
BF1
BF0
Off
2 Hz
1 Hz
0.5 Hz
0
0
1
1
0
1
0
1
BLINK MODE
BITA
Normal blinking
(1)
Alternation blinking
0
1
NUMBER OF DEVICES
MAXIMUM CONTACT
RESISTANCE
6000
2200
1200
700
2
3 to 5
6 to 10
11 to 16
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCF8533U | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal LCD driver for low multiplex rates |
| PCF8533U/2/F2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal LCD driver for low multiplex rates |
| PCF8533U/2/F2,026 | 功能描述:IC LCD DRIVER UNIV UNCASED DIE RoHS:是 類別:未定義的類別 >> 其它 系列:* 標準包裝:1 系列:* 其它名稱:MS305720A |
| PCF8533U/2/F2026 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
| PCF8533U/2/F2028 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
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