- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367817 > PCF84C84x (NXP Semiconductors N.V.) 8-BIT SINGLE CHIP MICROCONTROLLERS PDF資料下載
參數(shù)資料
| 型號： | PCF84C84x |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 145K |
| 代理商： | PCF84C84X |
Philips Semiconductors
The I
2
C serial bus: theory and practical consideration using Philips
low-voltage PCF84Cxx and PCD33xx
μ
C families
Application note
AN168
1988 Dec
7
The transfer is now complete – PCF8574 I/O Expandor will transfer
the serial data stream to its 8 output pins and latch them until further
update.
ACKWT:
MOV A,S1
;Get bus status word
;from S1.
;Poll the PIN bit
;until it goes low
;indicating transfer
;completed
;Jump to BUSERR
;routine if acknowledge
;not received.
;transfer complete,
;acknowledge received – return.
JB4 ACKWT
JBO BUSERR
RET
SL00950
Figure 4.
MASTER READS ONE BYTE FROM SLAVE
A read operation is a similar process; the address, however, will be
41H, the LSB indicating to the I/O device that a read is to be
performed. During the data portion of a read, the I/O port 8574 will
transmit the contents of its latches in response to the clock
generated by the master. The Master/Receiver in this case
generates a low-level acknowledge on reception of each byte (a
‘positive’ acknowledge). Upon completion of a read, the master
must generate a ‘negative’ acknowledge during the ninth clock to
indicate to the slaves that the read operation is finished. This is
necessary because an arbitrary number of bytes may be read within
the same transfer. A negative acknowledge consists of a high signal
on the data line during the ninth clock of the last byte to be read. To
accomplish this, the master must leave the acknowledge mode just
before the final byte, read the final byte (producing only 8 clock
pulses), program the bit-counter with 001 (preparing for a one-bit
negative acknowledge pulse), and simply move the contents of S0
to the accumulator. This final instruction accomplishes two things
simultaneously: it transfers the final byte to the accumulator and
produces one clock pulse on the SCL line. The structure of the
serial I/O register S0 is such that a read from it causes a
double-buffered transfer from the I
2
C bus to S0, while the original
contents of S0 are transferred to the accumulator. Because the
number of clocks produced on the bus is determined by the control
number in the Bit Counter, by presetting it to 001, only one
clock is generated. At this point in time the slave is still waiting for
an acknowledge; the bus is high due to the pull-up, as single clock
pulse in this condition is interpreted as a ‘negative’ acknowledge.
The slave has now been informed that reading is completed, a Stop
condition is now generated as before. The read process (one byte
from a slave with only a chip address) is shown in Figure 5.
These examples apply to a slave with a chip address – more than
one byte can be written/read within the same transfer; however, this
option is more applicable to I
2
C devices with sub-addresses such as
the static RAMs or Clock/Calendar. In the case of these types of
devices, a slightly different protocol is used. The RAM, for example,
requires a chip address and an internal memory location before it
can deliver or accept a byte of information. During a write operation,
this is done by simply writing the secondary address right after the
chip address – the peripheral is designed to interpret the second
byte as an internal address. In the case of a Read operation, the
slave peripheral must send data back to the Master after it has been
addressed and sub-addressed. To accomplish this, first the Start,
Address, and Sub-address is transmitted. Then we have repeated
start condition to reverse the direction of the data transfer, followed
by the chip address and RD, than a data string (w/acknowledges).
This repeated Start does not affect other peripherals – they have
been deactivated and will not reactivate until a Stop condition is
detected. I
2
C peripherals are equipped with auto-incrementing logic
which will automatically transmit or receive data in consecutive
(increasing) locations. For example, to read 3 consecutive bytes to
PCF8571 RAM locations 00, 01 and 02, we use the following format
as shown in Figure 7.
This routine reads the contents of location 00, 01 and 02 of the
PCF8570 256-byte RAM and puts them in registers R0, R1, and R2.
The auto-incrementing feature allows the programmer to indicate
only a starting location, then read an arbitrary block of consecutive
memory addresses. The WAIT 1 loop is required to poll for the
completion of the final byte because the ACKWT routine will not
recognize the negative acknowledge as a valid condition.
BUS ERROR CONDITIONS: ACKNOWLEDGE NOT
RECEIVED
In the above routines, should a slave fail to acknowledge, the
condition is detected during the ‘ACKWT’ routine. The occurrence
may indicate one of two conditions: the slave has failed to operate,
or a bus disturbance has occurred. The software response to either
event is dependent on the system application. In either case, the
‘BusErr’ routine should reinitialize the bus by issuing a ‘Stop’
condition. Provision may then be taken to repeat the transfer an
arbitrary number of times. Should the symptom persist, either an
error condition will be entered, or a backup device can be activated.
These sample routines represent single-master systems. A more
detailed analysis of multi-master/noisy environment systems are
treated in other application notes. For more complex systems, the
80C51 derivative microcontrollers with I
2
C interface are
recommended. Philips 80C51 micros implement a slightly modified
I
2
C interface and conventions, but operate in a similar fashion to the
micros described here. (See Philips Semiconductors AN430, “The
83/87C51/752 in a multi-master I
2
C environment”.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCF84C22AP | 8-bit microcontrollers |
| PCF84C22A | 8-bit microcontrollers |
| PCF84C42A | 8-bit microcontrollers |
| PCF84C42AP | 8-bit microcontrollers |
| PCF84C42AT | 8-bit microcontrollers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCF84C853AT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| PCF84C85A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Microcontroller with extended I/O |
| PCF84C85AP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Microcontroller with extended I/O |
| PCF84C85AT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Microcontroller with extended I/O |
| PCF84C85PN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。