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參數(shù)資料
| 型號： | PCF84C84x |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 145K |
| 代理商： | PCF84C84X |
Philips Semiconductors
The I
2
C serial bus: theory and practical consideration using Philips
low-voltage PCF84Cxx and PCD33xx
μ
C families
Application note
AN168
1988 Dec
5
arbitration. The resultant bus level will be low, and the loser will
withdraw from the bus and set its ‘Arbitration Lost’ flag (S1 bit 3).
The losing Master is now configured as a slave which could be
addressed during this very same cycle. These provisions allow for a
number of microcomputers to exist on the same bus. With properly
written subroutines, software for any one of the controllers may
regard other masters as transparent.
PCF84Cxxx
SCL
SDA
PCF8574
PCF8570
I/O EXPANDOR
ADDR = ’40’H
ADDR = ’A0’H
A
0
A
1
A
2
A
0
A
1
A
2
V
CC
SL00948
Figure 2. Schematic for Assembly Examples
I
2
C PROTOCOL AND ASSEMBLY LANGUAGE
EXAMPLES
I
2
C data transfers follow a well-defined protocol. A transfer always
takes place between a master and a slave. Currently a
microcomputer can be master or slave, while the ‘CLIPS’
peripherals are always slaves. In a ‘bus-free’ condition, both SCL
and SDA lines are kept logical high be external pull-up resistors. All
bus transfers are bounded by a ‘Start’ and a ‘Stop’ condition. A
‘Start’ condition is defined as the SDA line making a high-to-low
transition
while the SCL line is high
. At this point, the internal
hardware on all slaves are activated and are prepared to clock-in
the next 8 bits and interpret it as a 7-bit address and a R/W control
bit (MSB first). All slaves have an internal address (most have 2–3
programmable address bits) which is then compared with the
received address. The slave that recodnized its address will
respond by pulling the data line low during a ninth clock generated
by the master (all I
2
C byte transfers require the master to generate 8
clock pulses plus a ninth acknowledge-related clock pulse). The
slave-acknowledge will be registered by the master as a ‘0’
appearing in the LRB (Last Received Bit) position of the S1 serial
I/O status register. If this bit is high after a transfer attempt, this
indicates that a slave did not acknowledge and that the transfer
should be repeated.
After the desired slave has acknowledged its address, it is ready to
either send or receive data in response to the master’s driving clock.
All other slaves have withdrawn from the bus. In addition, for
multi-master systems, the start condition has set the ‘Bus Busy’ bit
of the serial I/O register S1 on all masters on the bus. This gives a
software indication to other master that the bus is in use and to wait
until the bus is free before attempting an access.
There are two types of I
2
C peripherals that now must be defined:
there are those with only a chip address such as the I/O expandor,
PCF8574, and those with a chip address plus an internal address
such as the static RAM, PCF8570. Thus after sending a start
condition, address, and R/W bit, we must take into account what
type of slave is being addressed. In the case of a slave with only a
chip address, we have already indicated its address and data
direction (R/W) and are therefore ready to send or receive data.
This is performed by the master generating bursts of 9 clock pulses
for each byte that is sent or received. The transaction for writing
one byte to a slave with a chip address only is shown in Figure 3.
In this transfer, all bus activity is invoked by writing the appropriate
control byte to the serial I/O control register S1, and by moving data
to/from the serial bus buffer register S0. Coming from a known state
(MOV S1, #18H-Slave, Receiver, Bus not Busy) we first load the
serial I/O buffer S0 with the desired slave’s address (MOV S0,
#40H). To transmit this preceded by a start condition, we must first
examine the control register S1, which, after initialization, looks like
this:
MAS-
TER TRANS
0
0
0
1
1
0
0
0
BUS
BUSY
PIN
ES0
BC2
BC1
BC0
To transmit to a slave, the Master, Transmitter, Bus Busy, PIN
(Pending Interrupt Not), and ESO (Enable Serial Output) must be
set to a 1. This results in an ‘F8H’ being written to S1. This word
defines the controller as a Master Transmitter, invokes the transfer
by setting the ‘Bus Busy’ bit, clears the Pending Interrupt Not (an
active low flag indicating the completion of a compete byte transfer),
and activates the serial output logic by setting the Enable Serial
Output (ESO) bit.
BIT COUNTER S12, S11, S10
BC2, BC1 and BC0 comprise a bit-counter which indicates to the
logic how long the word is to be clocked out over the serial data line.
By setting this to a 000H, we are telling
it to produce 9 clocks (8 bits plus an acknowledge clock) for this
transfer. The bit counter will then count off each bit as it is
transmitted. The bit counter possibilities are shown in NO TAG.
Thus, the bit counter keeps track of the number of clock pulses
remaining in a serial transfer. Additionally, there is a
not-acknowledge mode (controlled through bit 6 of clock control
register S2) which inhibits the acknowledge clock pulse, allowing the
possibility of straight serial transfer. We may thus define the word
size for a serial transfer (by pre-loading BC2, BC1, BC0 with the
appropriate control number), with or without an acknowledge-related
clock pulse being generated. This makes the controller able to
transmit serial data to most any serial device regardless of its
protocol (e.g., C-bus devices).
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相關(guān)代理商/技術(shù)參數(shù) |
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| PCF84C853AT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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| PCF84C85AT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Microcontroller with extended I/O |
| PCF84C85PN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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