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參數(shù)資料
| 型號： | PCF84C81A |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 145K |
| 代理商： | PCF84C81A |
Philips Semiconductors
The I
2
C serial bus: theory and practical consideration using Philips
low-voltage PCF84Cxx and PCD33xx
μ
C families
Application note
AN168
1988 Dec
3
EN SI
SERIAL
DATA I/O
(Pin 2)
I(Pin 17)
RESET
ES0
DIG. FILTER
DATA
CDATA
DATA
OUT S0
DATA IN
BUS
LOGIC
ARB.
DICLOCK
SCLK
BIT 7
S2
CLOCK
MULTIPLEXER
ACK ASC
PROGR. COUNTER
SYNC
L&
CONTROL
BIT 0
WR S2
S1
BIT 7
BIT 0
STATUS
INTERNAL CLOCK
WR S1
RD S1
MST TRX BB PIN
ES0
AL
BC2
AAS
BC1
ADO
BCO
LRB
INTERNAL MICROCOMPUTER BUS
LRB
AAS
AD0
PIN
INLOGIC
CLOCK CONTROL
REGISTER
SERIAL CLOCK PULSE GENERATOR
DATA SHIFT REGISTER
ADDRESS COMPARATOR
ADDRESS BACKUP LATCHES
ALS
BIT 7
BIT 0
INT REQ
S0‘
WR S0‘
WR S0
RD S0
WR ADDR. LATCHES
INT8400
LOGIC
BB
AL
SL00947
Figure 1. Block Diagram of the PCF84Cxxx I
2
C Interface
Data Shift Register S0 –
S0 is the data shift register used to
perform the conversion between serial and parallel data format. All
transmissions or receptions take place through register S0 MSB
first. All I
2
C bus receptions or transmissions involve moving data
to/from the accumulator from/to S0.
Address Register S0’ –
In multi-master systems, this register is
loaded with a controller’s slave address. When activated, (ALS = 0),
the hardware will recognize when it is being addressed by setting
the AAS (Addressed As Slave) flag. This provision allows a master
to be treated as a slave by other masters on the bus.
Status Register S1 – S1 is the bus status register. To control the
SIO interface, information is written to the register. The lower 4 bits
in S1 serve dual purposes; when written to, the control bits ES0,
BC2, BC1, BC0 are programmed (Enable Serial Output and a 3-bit
counter which indicates the current number of bits left in a serial
transfer). When reading the lower four bits, we obtain the status
information AL, AAS, AD0, LRB (Arbitration Lost, Addressed As
Slave, Address Zero (the general call has been received), the Last
Received Bit (usually the acknowledge bit)). The upper 4 bits are
the MST, TRX, BB and PIN control bits (Master, Transmitter, Bus
Busy, and Pending Interrupt Not). These bits define what role the
controller has at any particular time. The values of the master and
transmitter bits define the controller as either a master or slave (a
master initiates a transfer and generates the serial clock; a slave
does not), and as a transmitter or receiver. Bus Busy keeps track of
whether the bus is free or not, and is set and reset by the ‘Start’ and
‘Stop’ conditions which will be defined. Pending Interrupt Not is
reset after the completion of a byte transfer + acknowledge, and can
be polled to indicate when a serial transfer has been completed. An
alternative to polling the PIN bit is to enable the serial interrupt; upon
completion of a byte transfer, an interrupt will vector program control
to location 07H.
CLOCK CONTROL REGISTER (S2)
The clock control register of the PCF84Cxxx family defines the
frequency of f
SCLK
as the microcontroller clock frequency divided by
an integer (Table 2). It also defines ASC (asymmetrical clock) and
ACK (acknowledge).
If ASC=1, the generated SCLK has a duty cycle of about 75%. The
asymmetrical clock limites I
2
C bus transmission rate to below
55kHz. Divisors 39, 45 and 51 are not allowed if ASC=1. However,
an SCLK duty cycle of about 50% results if ASC=0. This permits
I
2
C bus transmission rates of up to 100kHz. All divisors of NO TAG
are available. Therefore, it is recommended to select ASC=0.
For the normal I
2
C bus protocol, ACK must be set. After each byte
transfer, an extra SCLK pulse is generated during which the receiver
may acknowledge reception. If ACK
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