參數(shù)資料
型號: PCF5079HK
廠商: NXP Semiconductors N.V.
英文描述: 3455RMG Series Phenolic Manual Reset Thermostats
中文描述: 3455RMG 系列酚醛手動重置恒溫器
文件頁數(shù): 9/28頁
文件大?。?/td> 146K
代理商: PCF5079HK
2001 Nov 21
9
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
7.7
Considerations for ramp-down
Referring to Fig.5, the i-th code can be programmed to
have either the CODE
END
or CODE
START
value or any
code between, depending on the application preferences.
Thesecodesdonotproduceanypowerattheoutputofthe
PA, as CODE
START
has been chosen to keep the PA
isolation. The proper conclusion of the ramp-down is
ensured by choosing CODE
END
< CODE
START
so that the
discharge of the integration capacitance is controlled until
the control voltage on pin VCD or VCG goes below the PA
conduction threshold and by applying at this time the PU
transition from logic 1 to logic 0.
At the beginning of a burst, the VDAC signal steps applied
at OP1 are not compensated by any signal at the sensor
input up to when pin VCD or VCG voltage is greater than
the PA conduction threshold voltage. In any case, the
initial DAC voltage steps are stored in the capacitance of
amplifier OP1. CODE
END
has to be chosen so that the
energy inside the shaded zone cancels the energy
accumulated in the summing node (OP1) at the start of a
burst and not balanced by a feedback signal at the sensor
input.
The exact value of the energy required depends on the
specific PA, on the characteristics of the overall loop and
on the values chosen for the settable parameters inside
the loop.
A rough idea can be derived with a simplified analysis of a
ramp-up, ramp-down cycle using the following
simplifications:
The starting conditions for OP1 and OP4 are biasing at
V
home
with zero charge on capacitances
The initial rising of pin VCD or VCG voltage from V
home
is caused only by the integration of the constant
CODE
KICK
VDAC is treated as applied directly at the summing
node, initially neglecting the transmission delay through
the internal low-pass filter.
Generally, the integrator OP4 input can be expressed as
V
in integrator
)
g
s
g
d
=
(1)
where g
s
and g
d
are respectively the gains of sensor input
and DAC input in the summing amplifier OP1.
Equation (1) holds for closed loop operation. In the time
interval between the rising of pin VCD or VCG voltage due
to CODE
KICK
(t = 0) and when V
conduction
for the PA is
reached (t = t
1
),
V
s
is 0 and operation is open loop. In this
time interval, a charge accumulates in the summing node,
which remains uncompensated.
Timet
1
canbecalculated with the precedingsimplification.
Now, to define the quantity
V
KICK
CODE
KICK
CODE
START
=
(2)
the current/voltage equations around the integrator OP4
can be solved by forcing the current through R1 to be
equal to the current through the integration capacitance
and calculating the
V generated on C
INT
, then
CINT
(3)
where
(4)
Substituting equation (4) into equation (3)
C
CINT
R1
×
(5)
Under the hypothesis the voltage is constant:
C
CINT
R1
×
(6)
Equation (6) can be used to calculate time t
1
at which the
conduction of the PA is reached, considering that
t
t
1
V
home
V
CINT
V
conduction
=
+
=
(7)
(8)
Time t
1
depends on the time constant of the integrator, by
the PA and by
V
KICK
. The condition to be fulfilled is that
the energy contained in the shaded zone (Fig.5) is at least
equal to the energy accumulated at the beginning:
t
1
(9)
where k is the number of quarter-bits during which
CODE
END
is applied.
V
s
×
V
VDAC
×
V
CINT
C
i
τ ) τ
d
0
t
×
=
i
τ )
g
------------------------------
V
R1
=
V
CINT
-------------1
g
0
t
d
×
V
KICK
×
d
τ
=
V
CINT
-------------1
g
d
×
V
KICK
×
t
×
=
t
1
R1
C
CINT
×
V
d
V
home
V
KICK
×
--------g
×
=
V
out
OP1
2
(t) dt = k
QB
CODE
END
CODE
START
(
)
2
×
×
0
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