參數(shù)資料
型號(hào): PCF2104L
廠商: NXP Semiconductors N.V.
英文描述: LCD controller/driver
中文描述: LCD控制器/驅(qū)動(dòng)器
文件頁數(shù): 23/56頁
文件大?。?/td> 366K
代理商: PCF2104L
1997 Dec 16
23
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
9.7
Set CGRAM address
‘Set CGRAM address’ sets bits 0 to 5 of the CGRAM
address (A
CG
in Table 3) into the Address Counter
(binary A[5] to A[0]). Data can then be written to or read
from the CGRAM.
Only bits 0 to 5 of the CGRAM address are set by the
‘Set CGRAM address’ instruction. Bit 6 can be set using
the ‘Set DDRAM address’ instruction or by using the
auto-increment feature during CGRAM write. All bits 0 to 6
can be read using the ‘Read busy flag and address’
instruction.
9.8
Set DDRAM address
Set DDRAM address sets the DDRAM address (A
DD
in
Table 3) into the Address Counter (binary A[6] to A[0).
Data can then be written to or read from the DDRAM.
Table 5
Hexadecimal address ranges
9.9
Read busy flag and address
‘Read busy flag and address’ reads the Busy Flag (BF).
When BF = logic 1 it indicates that an internal operation is
in progress. The next instruction will not be executed until
BF = logic 0, so BF should be checked before sending
another instruction.
At the same time, the value of the Address Counter
expressed in binary A[6] to A[0] is read out. The Address
Counter is used by both CGRAM and DDRAM and its
value is determined by the previous instruction.
9.10
Write data to CGRAM or DDRAM
Writes binary 8-bit data D[7] to D[0] to the CGRAM or the
DDRAM.
Whether the CGRAM or DDRAM is to be written to is
determined by the previous specification of CGRAM or
DDRAM address setting. After writing, the address
automatically increments or decrements by 1, in
accordance with the entry mode. Only bits D0 to D4 of
CGRAM data are valid, bits D5 to D7 are ‘don't care’.
ADDRESS
FUNCTION
00 to 4F
00 to 0B and 0C to 4F
00 to 27 and 40 to 67
00 to 13, 20 to 33, 40 to 53
and 60 to 73
1-line by 24
2-line by 12
2-line by 24
4-line by 12
9.11
Read data from CGRAM or DDRAM
Reads binary 8-bit data D[7] to D[0] from the CGRAM or
DDRAM.
The most recent ‘Set address’ instruction determines
whether the CGRAM or DDRAM is to be read.
The ‘Read data’ instruction gates the content of the data
register (DR) to the bus while E = HIGH. After E goes
LOW again, internal operation increments (or decrements)
the AC and stores RAM data corresponding to the new AC
into the DR.
Remark: the only three instructions that update the data
register (DR) are:
‘Set CGRAM address’
‘Set DDRAM address’
‘Read data’ from CGRAM or DDRAM.
Other instructions (e.g. ‘Write data, ‘Cursor/display shift’,
‘Clear display’, ‘Return home’) will not modify the data
register content.
10 INTERFACE TO MICROCONTROLLER
(PARALLEL INTERFACE)
The PCF2104x can send data in either two 4-bit operations
or one 8-bit operation and can thus interface to 4-bit or
8-bit microcontrollers.
In the 8-bit mode data is transferred as 8-bit bytes using
the 8 data lines DB0 to DB7. Three further control lines E,
RS, and R/W are required.
In the 4-bit mode data is transferred in two cycles of 4-bits
each. The higher order bits (corresponding to DB4 to DB7
in 8-bit mode) are sent in the first cycle and the lower order
bits (DB0 to DB3 in 8-bit mode) in the second cycle.
Data transfer is complete after two 4-bit data transfers.
It should be noted that two cycles are also required for the
Busy Flag check. 4-bit operation is selected by instruction.
See Figs 15, 16 and 17 for examples of bus protocol.
In the 4-bit mode pins DB3 to DB0 must be left
open-circuit. They are pulled up to V
DD
internally.
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