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參數(shù)資料
| 型號： | PCD8544 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 48 x 84 pixels matrix LCD controller/driver |
| 中文描述： | 48 × 84像素的矩陣液晶顯示控制器/驅(qū)動器 |
| 文件頁數(shù)： | 5/32頁 |
| 文件大小： | 154K |
| 代理商： | PCD8544 |
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1999 Apr 12
5
Philips Semiconductors
Product specification
48
×
84 pixels matrix LCD controller/driver
PCD8544
6
PINNING
Note
1.
For further details, see Fig.18 and Table 7.
6.1
Pin functions
6.1.1
R0
TO
R47
ROW DRIVER OUTPUTS
These pads output the row signals.
6.1.2
C0
TO
C83
COLUMN DRIVER OUTPUTS
These pads output the column signals.
6.1.3
V
SS1
, V
SS2
:
NEGATIVE POWER SUPPLY RAILS
Supply rails V
SS1
and V
SS2
must be connected together.
6.1.4
V
DD1
, V
DD2
:
POSITIVE POWER SUPPLY RAILS
Supply rails V
DD1
and V
DD2
must be connected together.
SYMBOL
DESCRIPTION
R0 to R47
C0 to C83
V
SS1
, V
SS2
V
DD1
, V
DD2
V
LCD1
, V
LCD2
T1
T2
T3
T4
SDIN
SCLK
D/C
SCE
OSC
RES
dummy1, 2, 3, 4 not connected
LCD row driver outputs
LCD column driver outputs
ground
supply voltage
LCD supply voltage
test 1 input
test 2 output
test 3 input/output
test 4 input
serial data input
serial clock input
data/command
chip enable
oscillator
external reset input
6.1.5
V
LCD1
, V
LCD2
: LCD
POWER SUPPLY
Positive power supply for the liquid crystal display. Supply
rails V
LCD1
and V
LCD2
must be connected together.
6.1.6
T1, T2, T3
AND
T4:
TEST PADS
T1, T3 and T4 must be connected to V
SS
, T2 is to be left
open. Not accessible to user.
6.1.7
SDIN:
SERIAL DATA LINE
Input for the data line.
6.1.8
SCLK:
SERIAL CLOCK LINE
Input for the clock signal: 0.0 to 4.0 Mbits/s.
6.1.9
D/C:
MODE SELECT
Input to select either command/address or data input.
6.1.10
SCE:
CHIP ENABLE
The enable pin allows data to be clocked in. The signal is
active LOW.
6.1.11
OSC:
OSCILLATOR
When the on-chip oscillator is used, this input must be
connected to V
DD
. An external clock signal, if used, is
connected to this input. If the oscillator and external clock
are both inhibited by connecting the OSC pin to V
SS
, the
display is not clocked and may be left in a DC state.
To avoid this, the chip should always be put into
Power-down mode before stopping the clock.
6.1.12
RES:
RESET
This signal will reset the device and must be applied to
properly initialize the chip. The signal is active LOW.
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