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參數(shù)資料
| 型號(hào)： | PCD6003U |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Digital telephone answering machine chip |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, UUC |
| 文件頁數(shù)： | 19/96頁 |
| 文件大小： | 385K |
| 代理商： | PCD6003U |
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2001 Apr 17
19
Philips Semiconductors
Product specification
Digital telephone answering machine chip
PCD6003
9.3
Real-Time Clock generation
The Real-Time Clock (RTC) divider provides a 1 minute
timing signal which is available as an interrupt to the
microcontroller. The RTC_CLK input clock is always
active, whether the PLL is active or not. Thus the complete
chip can be set into Power-down mode (but not System-off
mode), where the microcontroller can be woken up by the
RTC to maintain the values for date and time. The
RTC_CLK is directly derived from the EMG_CLK input
clock signal.
Figure 6 shows the RTC clock generation. To divide a
3.456 or a 3.580 MHz clock into a 1 minute RTC signal a
28 bit counter is required to count 60
×
3.456
×
10
6
clock
periods. To determine the number of most significant bits
ofthiscounterrequiredforanaccurateRTC,themaximum
allowed time deviation per month and the crystal accuracy
need to be taken into account. The LSB of the 28 counter
has an accuracy of 1/(60
×
3.456
×
10
6
) = 0.005
parts-per-million (ppm). Since a normal crystal accuracy is
about 10 ppm it is tolerable to have only the 17 MSB of the
counter available (10/0.005 = 2000, which implies that the
11 LSB can be disregarded), as shown in Fig.6.
If one month is set to 30
×
24
×
60
×
60 = 2.6
×
106
seconds, 10 ppm deviation equals 26 seconds per month
or about 5 minutes per year.
Since there are 2 possible RTC_CLK values, 3.580 and
3.456 MHz, there are 2 comparators selectable for the
RTC; COMP_3.580 and COMP_3.456. The nominal value
of these comparators are (11 LSB are set to logic 0):
COMP_3.580: CCD2800H (RTCON = A5H)
COMP_3.456: C5C1000H (RTCON = 82H).
In Section 9.2 the conditions for the RTC_MODE signal
are described.To allow connection of various crystals or
ceramicresonators,aswellastoprovideadjustmentofthe
RTC clock according to the crystal tolerance, 8 of the 17
most significant bits of the comparators are programmable
via the SFR register RTCON. The binary values of the
comparators are then as shown in Table 11.
Since the accuracy of Q11 is 10 ppm, with the adjustment
of the RTC via RTCON an accuracy of
±
5 ppm can be
achieved.ForanRTCpulseevery1 minutetheouterlimits
of the crystal frequency inputs which can be connected
are:
COMP_3.580 (max): CCFF800H
→
3.582600 MHz
COMP_3.580 (min): CC80000H
→
3.573897 MHz.
COMP_3.456 (max): C5FF800H
→
3.460267 MHz
COMP_3.456 (min): C580000H
→
3.451563 MHz.
The default value of RTCON for an input frequency
3.58 MHz is A5H and for an input frequency of 3.456 MHz
is 82H.
Table 11
Comparator contents
Q27
Q18
Q11
COMP_3.580
COMP_3.456
1
1
1
1
0
0
0
0
1
0
1
1
0
0
0
1
1
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
bit 7
←
RTCON
→
bit 0
handbook, full pagewidth
MGM770
17
17
17
Q11 to Q27
EMG_CLK
Q10
Q0
28 BIT
RIPPLE
COMP_3.456
COMP_3.580
0
1
RTC_MODE
0: RTC_CLK = 3.456 MHz
1: RTC_CLK = 3.580 MHz
synch_reset
RTC_event
Fig.6 Real-Time Clock (RTC) generation.
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