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參數(shù)資料
| 型號(hào)： | PCD5043 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | DECT burst mode controller |
| 中文描述： | 無繩突發(fā)模式控制器 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 109K |
| 代理商： | PCD5043 |
1996 Oct 31
15
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5043
6.6.3
W
ATCHDOG
The PCD5043 is equipped with a watchdog timer, which
generates a reset towards an external device (e.g. a
μ
C)
after time-out. Two (fixed) time-out periods can be
programmed; 1.25 s and 82 s. The watchdog function can
be disabled by using the EN_WATCHDOG input pin.
6.6.4
P
OWER
-
DOWN
The PCC may switch off the 6.912 MHz internal clock, to
enter a power saving mode. All blocks, running on this
clock are then switched off (i.e. RF-interface, cipher block,
speech interface, PCC). This is called the power-down
state, and is only used in the handset mode.
The 13.824 MHz clock is never switched off. The Timing
Control, microcontroller interface, and Bus Controller keep
running, in order to remain synchronous with a base
station, and to keep the wake-up circuitry active. During
power-down the external microcontroller has still access to
the common data area.
6.7
Survey of registers
For a survey of all addresses occupied refer to
Tables 1 and 2. Some of the address locations are used
differently for read and write. The addresses 000 to 7DF
are occupied by RAM memory, while the upper 32 bytes
are assigned to the hardware registers. A part of the RAM
memory is allocated for use by the RF block, cipher block,
and the speech interface.
Table 1
Hardware register addresses
ADDRESS
WRITE
READ
7E0
7E1
7E2
7E3
7E4
7E5
7E6
7E7
7E8
7E9
7EA
7EB
7EC
7ED
7EE
7EF
7F0
7F1
7F2
7F3
7F4
7F5
7F6
7F7
7F8
7F9
7FA
7FB
7FC
7FD
7FE
7FF
S-DATA1
S-DATA2
S-DATA3
B-field-shift
B-field-loc.
A-field-loc.
window-wide-off
window-wide-on
window-narrow-off
window-narrow-on
T-power-rmp-on
synth-off
RF-control-port
slot-cnt-off
frame-cnt-ref
sync-ref-preset
bit-counter-preset
frame-counter
slot-counter
sync-control
BMC-mode
correlator-threshold measure
watchdog-1
watchdog-2
interrupt-event
interrupt-enable
interrupt-reset
controller mode
RMT-STAT
RF-STATUS
sync-status
slot-counter-copy
RSSI
bit-counter-copy1
bit-counter-copy2
frame-counter
slot-counter
sync-control
BMC-mode
interrupt-event
interrupt-enable
controller mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCD5043H | DECT burst mode controller |
| PCD5091HZ | DECT baseband controller |
| PCD5091 | DECT baseband controller |
| PCD5091H | DECT baseband controller |
| PCD5092 | DECT baseband controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCD5043H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DECT burst mode controller |
| PCD5071 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MODEM |
| PCD5090 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DECT baseband controllers |
| PCD5090H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DECT baseband controllers |
| PCD5090H232F1 | 制造商:PHILIPS 功能描述:* |
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