參數(shù)資料
型號: PCD5042HZ
廠商: NXP SEMICONDUCTORS
元件分類: 無繩電話/電話
英文描述: DECT burst mode controller
中文描述: TELECOM, CORDLESS, BURST MODE CONTROLLER, PQFP80
文件頁數(shù): 4/28頁
文件大?。?/td> 134K
代理商: PCD5042HZ
1996 Oct 31
4
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5042
4
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
MBH741
RF INTERFACE
PROGRAMMABLE
COMMUNICATION
CONTROLLER (PCC)
DATA MEMORY
2 kbyte RAM
TIMING, CONTROL,
CLOCK
GENERATION
PCC
PROGRAM MEMORY
4 kbyte ROM
MICROCONTROLLER
INTERFACE
SPEECH
INTERFACE
internal
bus
PCD5042
DECT
BURST MODE
CONTROLLER
to CODEC/
Highway
3-wire synthesizer
interface
Rx/Tx data
8051/68000
interface
5
PINNING
(see Figs 2 and 3)
SYMBOL
PIN
TYPE
(2)
DESCRIPTION
QFP64
LQFP80
(1)
AD0 to AD7
1 to 8
80, 1, and
3 to 7
9
11
14 to 12
15
16
I/O
address/Data bus
ALE
CS
A8 to A10
V
DD1
PROC_CLK
9
I
I
I
address latch enable
chip select (active LOW)
address bus
positive supply 1
microcontroller clock; programmable from f
CLK
/64 to f
CLK
,
where f
CLK
is the crystal oscillator frequency
negative supply 1
crystal oscillator input
crystal oscillator output
negative supply
watchdog timer output; intended to reset the external
microcontroller when expired
read (active LOW)
write (active LOW)
ready signal (active LOW), to initiate wait states in the
microcontroller (open drain)
10
13 to 11
14
15
P
O
V
SS1
XTAL1
XTAL2
V
SS2
RESET_OUT
16
17
18
19
20
17
20
21
22
23
P
I
O
P
O
RD
WR
RDY
21
22
23
24
25
26
I
I
O
相關(guān)PDF資料
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