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參數(shù)資料
| 型號： | PCD5002H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 尋呼電路 |
| 英文描述： | Advanced POCSAG and APOC-1 Paging Decoder |
| 中文描述： | TELECOM, PAGING DECODER, PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32 |
| 文件頁數(shù)： | 31/48頁 |
| 文件大?。?/td> | 203K |
| 代理商： | PCD5002H |
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1997 Jun 24
31
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
Table 30
Identifier bit allocation
Notes
1.
The bit numbering corresponds with the numbering in a POCSAG codeword; bit 1 is the flag bit (0 = address,
1 = message).
A UPSW needs 18 bits to be matched for successful identification. Bit 1 (MSB) must be logic 0. Bits 2 to 19 contain
the identifier bit pattern, they are followed by 2 predetermined random (function) bits and the UPSW is completed by
10 CRC error correction bits and an even-parity bit.
Bits FR3 to FR1 (MSB: FR3) contain the 3 least significant bits of the 21-bit RIC.
Identifiers 1 and 2 (RIC only) will be disabled by programming bit D2 as logic 0.
2.
3.
4.
Table 31
Identifier types
BYTE
BIT (MSB: D7)
DESCRIPTION
1
2
D7 to D0
D7 to D0
D7 and D6
D5
D4
D3
D2
D1
D0
bits 2 to 9 of POCSAG codeword (RIC or UPSW); notes 1 and 2
bits 10 to 17
bits 18 and 19
frame number bit FR3 (RIC); note 3
frame number bit FR2 (RIC)
frame number bit FR1 (RIC)
identifier type selection (0 = UPSW, 1 = RIC); note 4
identifier enable (1 = enabled)
batch zero ID/continuous decoding (1 = enabled)
3
BYTE 3, BIT D2
BYTE 3, BIT D0
DESCRIPTION
0
0
1
1
0
1
0
1
user programmable sync word (UPSW)
continuous data decoding (CDD) sync word
normal user address (RIC)
batch zero identifier
8.59
Voltage doubler
An on-chip voltage doubler provides an unregulated DC
output for supplying an LCD or a low power microcontroller
at output V
PO
. An external ceramic capacitor of 100 nF
(typ.) is required between pins CCN and CCP. The voltage
doubler is enabled via SPF programming.
8.60
Level-shifted interface
All interface lines are suited for communication with a
microcontroller operating from a higher supply voltage.
The external device must have a common reference at V
SS
of the PCD5002.
The reference voltage for the level-shifted interface must
be applied to input V
PR
. If required this could be the
on-chip voltage doubler output V
PO
. When the
microcontroller has a separate (regulated) supply it should
be connected to V
PR
.
The level-shifted interface lines are RST, DON, ALC, REF
and INT.
The I
2
C-bus interface lines SDA and SCL can be
level-shifted independently of V
PR
by the standard external
pull-up resistors.
8.61
Signal test mode
A special ‘signal test’ mode is available for monitoring the
performance of a receiver circuit together with the
front-end of the PCD5002.
For this purpose the output of the digital noise filter and the
recovered bit clock are made available at outputs REF and
INT respectively. All synchronization and decoding
functions are normally active.
The ‘signal test’ mode is activated/deactivated by SPF
programming.
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PDF描述 |
|---|---|
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| PCB1 | Fuse |
| PCB2 | Fuse |
| PCB2.5 | Fuse |
| PCB3 | Fuse |
相關代理商/技術參數(shù) |
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| PCD5002HBD-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5002HBD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5002U/10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG and APOC-1 Paging Decoder |
| PCD5003 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG Paging Decoder |
| PCD5003A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Pager Decoder for POCSAG |
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