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| 型號： | PCD5002H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 尋呼電路 |
| 英文描述： | Advanced POCSAG and APOC-1 Paging Decoder |
| 中文描述： | TELECOM, PAGING DECODER, PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32 |
| 文件頁數(shù)： | 19/48頁 |
| 文件大?。?/td> | 203K |
| 代理商： | PCD5002H |
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1997 Jun 24
19
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
Fig.8 Message types.
handbook, full pagewidth
n bytes with acknowledge
FROM
MASTER
FROM
SLAVE
A
A
S
SLAVE ADDRESS
R/W
DATA
A
DATA
A
P
S = START condition
P = STOP condition
A = Acknowledge
N = Not acknowledge
n bytes with acknowledge
A
S
SLAVE ADDRESS
R/W
DATA
DATA
P
A
(a)
(b)
(c)
R/W
DATA
SL. ADR.
SL. ADR.
R/W
DATA
0 (write)
0 (write)
1 (read)
1 (read)
index
address
index
address
n bytes with
acknowledge
n bytes with
acknowledge
change of direction
N
A
A
A
INDEX
INDEX
A
S
S
N
P
MLC250
(a) Master writes to slave.
(b) Master reads from slave.
(c) Combined format (shown: write plus read).
8.25
Decoder I
2
C-bus access
All internal access to the PCD5002 takes place via the
I
2
C-bus interface. For this purpose the internal registers,
SRAM and EEPROM have been memory mapped and are
accessed via an
index register
. Table 16 shows the index
addresses of all internal blocks.
Registers are addressed directly, while RAM and
EEPROM are addressed indirectly via address pointers
and I/O registers.
Remark
: The EEPROM memory map is non-contiguous
and is organized as a matrix.
The EEPROM address pointer contains both row and
column indicators.
Data written to read-only bits will be ignored. Values read
from write-only bits are undefined and must be ignored.
Each I
2
C-bus write message to the PCD5002 must start
with its slave address, followed by the index address of the
memory element to be accessed. An I
2
C-bus read
message uses the last written index address as a data
source. The different I
2
C-bus message types are shown in
Fig.8.
As a slave the PCD5002 cannot initiate bus transfers by
itself. To prevent an external controller from having to
monitor the operating status of the decoder, all important
events generate an external interrupt on output INT.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCD5 | Fuse |
| PCB1 | Fuse |
| PCB2 | Fuse |
| PCB2.5 | Fuse |
| PCB3 | Fuse |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCD5002HBD-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5002HBD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5002U/10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG and APOC-1 Paging Decoder |
| PCD5003 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG Paging Decoder |
| PCD5003A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Pager Decoder for POCSAG |
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