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參數資料
| 型號： | PCD4440T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Analog voice scrambler/descrambler |
| 中文描述： | TELECOM, CORDLESS, SCRAMBLER/DESCRAMBLER, PDSO8 |
| 封裝： | 7.50 MM, PLASTIC, SOT-176-1, SOP-8 |
| 文件頁數： | 8/20頁 |
| 文件大小： | 105K |
| 代理商： | PCD4440T |
1996 Dec 20
8
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
PCD4440T
7.5
Serial clock input (SCL), Serial data input
(SDA)
SCL and SDA are serial clock and data lines which
conform to the I
2
C-bus specification. Both inputs must be
pulled up externally to V
DD
through resistors of
approximately 10 k
.
7.6
Address input (A0)
A0 is the slave address input and is used to set one bit of
the slave address, so as to identify one of two PCD4440T
devices connected to the same I
2
C-bus. Whether another
PCD4440T is connected to the bus or not, A0 must be
connected to V
DD
or V
SS
. The remaining bits of the slave
address are fixed internally.
7.7
I
2
C-bus data configuration
The PCD4440T is always a slave receiver in the I
2
C-bus
configuration (the R/W bit = 0). The slave address consists
of 7 bits, where the least significant is set by the input on
A0. The more significant bits are fixed internally, as shown
in Fig.5. For definition of D0-D4, see Table 1.
7.8
Signal input (IN), Signal output (OUT)
Signal input for the scrambler/descrambler is coupled into
a ‘Sallen and Key’ anti-aliasing filter configuration. A DC
bias voltage of
1
2
V
DD
is built-in.
The analog signal output is buffered to achieve a relatively
low output impedance of roughly 1 k
which is sufficient to
drive the earpiece amplifier or similar applications.
handbook, full pagewidth
MGG732
S
1
1
0
1
1
1
A0
0
A
0
0
0
0
D3
D2
D1
D0
A
P
slave address
data
R/W
MSB
acknowledge
acknowledge
internal STROBE
Fig.5 I
2
C-bus data format.
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