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參數(shù)資料
| 型號(hào)： | PCD3360 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Programmable multi-tone telephone ringer |
| 中文描述： | 可編程多音頻電話鈴聲 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 117K |
| 代理商： | PCD3360 |
1997 Jan 15
5
Philips Semiconductors
Product specification
Programmable multi-tone telephone ringer
PCD3360
7
FUNCTIONAL DESCRIPTION
(see Fig.1)
7.1
Supply pins (V
DD
and V
SS
)
If the supply current (V
DD
) drops below the standby voltage
(V
stb
), the oscillator and most other functions are switched
off and the supply current is reduced to the standby current
(I
stb
). The automatic swell register retains its information
until V
DD
drops further to a value V
AS
at which reset
occurs.
7.2
Oscillator (OSC)
The 64 kHz oscillator is operated via an external resistor
and capacitor connected to pin OSC (see Fig.8).
The oscillator signal is divided by two to provide the32 kHz
internal system clock.
7.3
Selection pin input circuit
(see Fig.3)
Pins FDE, RR1, RR2, DM, IS1, IS2, TS1, TS2, FL and FH
are pulled down internally by a pull-down current I
IH
when
they are connected to V
DD
and by a pull-down resistance
R
IL
when they are connected to V
SS
. Thus when the pins
are open-circuit they are defined LOW. Therefore only a
single-contact switch is required to connect the pins to
V
DD
; yet the supply current is only marginally increased as
I
IH
is very small.
Fig.3 Input circuit of selection pins.
(1) Transistor resistance is R
IL
when switched on.
FDE
RR1
RR2
DM
IS1
IS2
TS1
TS2
FL
FH
selection
pins
IIH
VSS
MGD709
PCD3360
(1)
7.4
Frequency discriminator circuit (FDE and FDI)
The frequency discriminator circuit prevents the ringer
being activated unintentionally by dial pulses, speech or
other invalid signals.
The circuit is enabled or disabled by input FDE. WhenFDE
is LOW and V
DD
> V
stb
, the circuit is enabled and FDI acts
as the input for ringing frequency detection. When FDE is
HIGH, the circuit is disabled and FDI becomes the
enable/disable input for tone sequence generation.
When the circuit is enabled, it starts to produce output
ringing tones after one cycle of an appropriate input
frequency is detected at FDI. An input cycle is detected
when either 2 rising or 2 falling edges are received, and
this implies a delay of between 1 and 1.5 input cycles
before output ringing begins. The allowed input frequency
range is set by the states of pins FL and FH, as shown in
Table 2. Output ringing continues for as long as valid input
ringing frequency is detected.
FDI has a Schmitt-trigger action; the levels are set by an
external resistor R2 (see Fig.8) and an internal sink current
that is switched from 20
μ
A (typ.) for FDI = LOW to <0.1
μ
A
for FDI = HIGH. Excess current entering FDI via R2 is
absorbed by internal diodes clamped to V
DD
and V
SS
.
7.5
Selection of frequency discriminator limits
(FL and FH)
With the frequency discriminator enabled (V
DD
> V
stb
and
FDE = LOW) the lower and upper limits of the input
frequency are set by the inputs FL and FH as shown by
Table 2.
Table 2
Selection of lower and upper frequency
discriminator limits (f
OSC
= 64 kHz)
FL INPUT
STATE
LOWER
LIMIT
FH INPUT
STATE
UPPER
LIMIT
LOW
HIGH
20 Hz
13.3 Hz
LOW
HIGH
60 Hz
30 Hz
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