參數(shù)資料
型號(hào): PCA9561
廠商: NXP Semiconductors N.V.
英文描述: Quad 6-bit multiplexed I2C EEPROM DIP switch
中文描述: 四6位多路復(fù)用的I2C EEPROM的DIP開(kāi)關(guān)
文件頁(yè)數(shù): 7/17頁(yè)
文件大?。?/td> 111K
代理商: PCA9561
Philips Semiconductors
Product data
PCA9561
Quad 6-bit multiplexed I
2
C EEPROM DIP switch
2003 Jun 27
7
CHARACTERISTICS OF THE I
2
C-BUS
The I
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line
(SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may
be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as
changes in the data line at this time will be interpreted as control signals (see Figure 3).
SDA
SCL
SW00363
data line
stable;
data valid
change
of data
allowed
Figure 3. Bit transfer
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined
as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 4).
System configuration
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device initiates a transfer is the ‘master’ and the
devices which are controlled by the master are the ‘slaves’ (see Figure 5).
SDA
SCL
SW00365
S
P
SDA
SCL
START condition
STOP condition
Figure 4. Definition of start and stop conditions
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
SW00366
I
2
C
MULTIPLEXER
SLAVE
Figure 5. System configuration
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