參數(shù)資料
型號: PCA9559
廠商: NXP Semiconductors N.V.
英文描述: 5-bit multiplexed/1-bit latched 6-bit I I C EEPROM(5位多路的/1位鎖存的6位IIC EEPROM)
中文描述: 5位multiplexed/1-bit鎖存6位國際進口的EEPROM(5位多路的/ 1位鎖存的6位國際進口的EEPROM)
文件頁數(shù): 7/10頁
文件大?。?/td> 101K
代理商: PCA9559
Philips Semiconductors
Product specification
PCA9559
5-bit multiplexed/1-bit latched 6-bit I
2
C EEPROM
2000 Jan 31
7
AC CHARACTERISTICS
SYMBOL
PARAMETER
LIMITS
TYP.
UNIT
MIN.
MAX.
MUX_in
MUX_out
T
plh
T
phl
Select
MUX_out
T
plh
T
phl
Override
Non-MUX_out
T
plh
T
phl
Override
MUX_out
T
plh
T
phl
T
R
T
F
P
F
C
L
I
2
C Bus
28
37
nS
16
21
nS
30
39
nS
17
22
nS
34
43
nS
19
25
nS
31
41
nS
21
27
nS
Output rise time
1.0
3
ns/V
Output fall time
1.0
3
ns/V
Pull-up resistor for outputs
1.0
ns/V
Test load capacitance on outputs
pF
t
SCL
t
BUF
SCL clock frequency
10
400
kHz
μ
s
Bus free time between a STOP and a START condition
1.3
t
HD:STA
Hold time (repeated) START condition. After this period, the first
clock pulse is generated
LOW period of SCL clock
600
ns
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
SP
t
SU:STO
t
R
t
I
C
L
T
W
1.3
μ
s
ns
HIGH period of SCL clock
600
–12
Set-up time for a repeated START condition
600
–32
ns
Data hold time
0
10
ns
Data set-up time
100
–100
ns
Data spike time
0
50
ns
Set-up time for STOP condition
600
10
ns
Rise time for both SDA and SCL signals (10 – 400 pF bus)
20
300
ns
Fall time for both SDA and SCL signals (10 – 400 pF bus)
20
300
ns
Capacitive load for each bus line
Write cycle time
1
400
pF
15
mS
NOTE:
1. WRITE CYCLE time can only be measured indirectly during the write cycle. During this time, the device will not acknowledge its I
2
C Address.
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