參數(shù)資料
型號(hào)： PCA9535ECDWR2G
廠商： ON Semiconductor
文件頁(yè)數(shù)： 3/20頁(yè)
文件大?。?/td> 0K
描述： 16-BIT I/O EXPANDER
標(biāo)準(zhǔn)包裝： 1,000
接口： I²C 總線，SM 總線
輸入/輸出數(shù)： 16
中斷輸出： 是
頻率 - 時(shí)鐘： 100kHz
電源電壓： 1.65 V ~ 5.5 V
工作溫度： -55°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC
包裝： 帶卷 (TR)
包括： *
PCA9535E, PCA9535EC
http://onsemi.com
11
BUS TRANSACTIONS
Writing to the Port Registers
To transmit data to the PCA9535E/PCA9535EC, the bus
master must first send the device address with the least
significant bit set to logic 0 (see Figure 5 “PCA9535E and
PCA9535EC device address”). The command byte is sent
after the address and determines which registers will receive
the data following the command byte.
There
are
eight
registers
within
the
PCA9535E/PCA9535EC. These registers are configured to
operate as four register pairs: Input Ports, Output Ports,
Polarity Inversion Ports, and Configuration Ports. Data
bytes are sent alternately to each register in a register pair
(see Figures 6 and 7). For example, if one byte is sent to
Output Port 1 (register 3), then the next byte will be stored
in Output Port 0 (register 2). There is no limitation on the
number of data bytes sent in one write transmission. In this
way, each 8bit register may be updated independently of
the other registers.
Figure 6. Write to Output Port Registers
A2 A1 A0 0 A
S A6
START condition
R/W acknowledge
from slave
A
SCL
SDA
A
write to port
data out
from port 0
P
tv(Q)
9
8
7
6
5
4
3
2
1
command byte
data to port 0
DATA 0
slave address
0
STOP
condition
0.0
0.7
acknowledge
from slave
acknowledge
from slave
data to port 1
DATA 1
1.0
1.7
A
data out
from port 1
tv(Q)
DATA VALID
A5 A4 A3
0 0 0 0 0 1 0
Figure 7. Write to Configuration Registers
A2 A1 A0 0 A
S A6
START condition
R/W acknowledge
from slave
A
SCL
SDA
AP
9
8
7
6
5
4
3
2
1
command byte
data to register
DATA 0
slave address
0
STOP
condition
LSB
MSB
acknowledge
from slave
acknowledge
from slave
data to register
DATA 1
LSB
MSB
A
A5 A4 A3
0 0 0
1 1 0
0
Reading the Port Registers
To read data from the PCA9535E/PCA9535EC, the bus
master must first send the PCA9535E/PCA9535EC address
with the least significant bit set to logic 0 (see Figure 5
“PCA9535E and PCA9535EC device address”). The
command byte is sent after the address and determines
which register will be accessed.
After a restart, the device address must be sent again, but
this time, the least significant bit is set to logic 1. Data from
the register defined by the command byte will then be sent
by the PCA9535E/PCA9535EC (see Figures 8, 9 and 10).
Data is clocked into the register on the falling edge of the
acknowledge clock pulse. After the first byte is read,
additional bytes may be read but with data alternately
coming from each register in the pair. For example, if you
read Input Port 1, then the next byte read would be
Input Port 0. There is no limitation on the number of data
bytes received in one read transmission but the bus master
must not acknowledge the data for the final byte received.
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