參數(shù)資料
型號: PCA9534APWRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 8 I/O, PIA-GENERAL PURPOSE, PDSO16
封裝: GREEN, PLASTIC, TSSOP-16
文件頁數(shù): 18/41頁
文件大?。?/td> 985K
代理商: PCA9534APWRG4
V
CC
V
POR
V
PORF
Time
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Time
www.ti.com
SCPS141F – SEPTEMBER 2006 – REVISED JUNE 2010
Figure 20. VPOR
Interrupt Requirements
The expected performance of the interrupt feature is that INT is to be cleared (de-asserted) when the input
register is read or all inputs return to the last read values. INT is also de-asserted when both of the following
occur:
The last I2C command byte (register pointer) written was 00h. This generally means the last operation with
the device was a read of the input register, but the command byte may have been written with 00h without
ever going on to read the Input register.
Any other slave device on the I2C bus acknowledges an address byte with the R/W bit set high. This occurs
when reading any other valid device on the bus.
In order to prevent INT from de-asserting when another device is read on the I2C bus, the user needs to change
the command byte to something other than 00 (hex) after a read operation to the device.
Copyright 2006–2010, Texas Instruments Incorporated
25
Product Folder Link(s): PCA9534A
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