參數(shù)資料
型號: PCA9534APWRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 8 I/O, PIA-GENERAL PURPOSE, PDSO16
封裝: GREEN, PLASTIC, TSSOP-16
文件頁數(shù): 17/41頁
文件大小: 985K
代理商: PCA9534APWRG4
VCC
Ramp-Up
Time to Re-Ramp
Time
Ramp-Down
VIN drops below POR levels
VCC_RT
VCC_FT
VCC_TRR_VPOR50
V
CC
Time
V
CC_GH
V
CC_GW
SCPS141F – SEPTEMBER 2006 – REVISED JUNE 2010
www.ti.com
Figure 18. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Table 10 specifies the performance of the power-on reset feature for PCA9534A for both types of power-on
reset.
Table 10. RECOMMENDED SUPPLY SEQUENCING AND RAMP RATES(1)
PARAMETER
MIN
TYP
MAX
UNIT
VCC_FT
Fall rate
1
100
ms
VCC_RT
Rise rate
0.01
100
ms
VCC_TRR_GND
Time to re-ramp (when VCC drops to GND)
0.001
ms
VCC_TRR_POR50
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)
0.001
ms
Level that VCCP can glitch down to, but not cause a functional
VCC_GH
1.2
V
disruption when VCCX_GW = 1 ms
Glitch width that will not cause a functional disruption when
VCC_GW
ms
VCCX_GH = 0.5 × VCCx
VPORF
Voltage trip point of POR on falling VCC
0.767
1.144
V
VPORR
Voltage trip point of POR on fising VCC
1.033
1.428
V
(1)
TA = –40°C to 85°C (unless otherwise noted)
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 19 and Table 10 provide more
information on how to measure these specifications.
Figure 19. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 20 and Table 10 provide more details on this specification.
24
Copyright 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): PCA9534A
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