參數(shù)資料
型號: PCA9506DGG,518
廠商: NXP Semiconductors
文件頁數(shù): 33/34頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 40B 56TSSOP
標準包裝: 2,000
接口: I²C
輸入/輸出數(shù): 40
中斷輸出:
頻率 - 時鐘: 400kHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 帶卷 (TR)
包括: POR
其它名稱: 935280798518
PCA9506DGG-T
PCA9506DGG-T-ND
PCA9505_9506
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 3 August 2010
8 of 34
NXP Semiconductors
PCA9505/06
40-bit I2C-bus I/O port with RESET, OE and INT
The lowest 6 bits are used as a pointer to determine which register will be accessed. The
registers are:
IP: Input Port registers (5 registers)
OP: Output Port registers (5 registers)
PI: Polarity Inversion registers (5 registers)
IOC: I/O Configuration registers (5 registers)
MSK: Mask interrupt registers (5 registers)
If the Auto-Increment flag is set (AI = 1), the 3 least significant bits are automatically
incremented after a read or write. This allows the user to program and/or read the
5 register banks sequentially.
If more than 5 bytes of data are written and AI = 1, previous data in the selected registers
will be overwritten. Reserved registers are skipped and not accessed (refer to Table 3).
If the Auto-Increment flag is cleared (AI = 0), the 3 least significant bits are not
incremented after data is read or written. During a read operation, the same register bank
is read each time. During a write operation, data is written to the same register bank each
time.
Only a Command register code with the 5 least significant bits equal to the 25 allowable
values as defined in Table 3 are valid. Reserved or undefined command codes must not
be accessed for proper device functionality. At power-up, this register defaults to 0x80,
with the AI bit set to logic 1, and the lowest 7 bits set to logic 0.
During a write operation, the PCA9505/06 will acknowledge a byte sent to OPx, PIx, and
IOCx and MSKx registers, but will not acknowledge a byte sent to the IPx registers since
these are read-only registers.
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