參數(shù)資料
型號(hào): PCA9505DGG,118
廠商: NXP Semiconductors
文件頁(yè)數(shù): 16/34頁(yè)
文件大小: 0K
描述: IC I/O EXPANDER I2C 40B 56TSSOP
標(biāo)準(zhǔn)包裝: 2,000
接口: I²C
輸入/輸出數(shù): 40
中斷輸出:
頻率 - 時(shí)鐘: 400kHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 帶卷 (TR)
包括: POR
其它名稱(chēng): 935284486118
PCA9505DGG-T
PCA9505DGG-T-ND
PCA9505_9506
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 3 August 2010
23 of 34
NXP Semiconductors
PCA9505/06
40-bit I2C-bus I/O port with RESET, OE and INT
[1]
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held
LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.
[2]
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[3]
tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[4]
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region SCL’s falling edge.
[5]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified tf.
[6]
Cb = total capacitance of one bus line in pF.
[7]
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
Reset
tw(rst)
reset pulse width
4
-
4
-
ns
trec(rst)
reset recovery time
0
-
0
-
ns
trst
reset time
100
-
100
-
ns
Table 11.
Dynamic characteristics …continued
Symbol
Parameter
Conditions
Standard mode
I2C-bus
Fast mode I2C-bus
Unit
Min
Max
Min
Max
Fig 16. Definition of timing on the I2C-bus
tSP
tBUF
tHD;STA
P
S
tLOW
tr
tHD;DAT
tf
tHIGH
tSU;DAT
tSU;STA
Sr
tHD;STA
tSU;STO
SDA
SCL
002aaa986
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