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參數(shù)資料
| 型號(hào)： | PC826 |
| 廠商： | Sharp Corporation |
| 英文描述： | Hgh -w=der Vtige, Hgh Density Mounting Type Photocoupler |
| 中文描述： | 杭州到瓦特\u003d德Vtige，生長激素密度安裝類型光電耦合 |
| 文件頁數(shù)： | 37/59頁 |
| 文件大?。?/td> | 455K |
| 代理商： | PC826 |
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37
PC8265A PowerQUICC II
5336A–HIREL–08/03
Layout Practices
Each pin should be provided with a low-impedance path to the board’s power supply.
Each ground pin should likewise be provided with a low-impedance path to ground. The
power supply pins drive distinct groups of logic on the chip. The power supply should be
bypassed to ground using at least four 0.1 μF by-pass capacitors located as close as
possible to the four sides of the package. The capacitor leads and associated printed
circuit traces connecting to the chip and ground should be kept to less than half an inch
per capacitor lead. A four-layer board is recommended, employing two inner layers as
GND planes.
All output pins on the PC8265A have fast rise and fall times. Printed circuit (PC) trace
interconnection length should be minimized in order to minimize overdamped conditions
and reflections caused by these fast output switching times. This recommendation par-
ticularly applies to the address and data buses.
Maximum PC trace lengths of six inches are recommended. Capacitance calculations
should consider all device loads as well as parasitic capacitances due to the PC traces.
Attention to proper PCB layout and bypassing becomes especially critical in systems
with higher capacitive loads because these loads create higher transient currents in the
GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special
care should be taken to minimize the noise levels on the PLL supply pins.
Table 7 provides preliminary, estimated power dissipation for various configurations.
Note that suitable thermal management is required for conditions above P
D
= 3W (when
the ambient temperature is 70
°
C or greater) to ensure the junction temperature does not
exceed the maximum specified value. Also note that the I/O power should be included
when determining whether to use a heat sink.
Notes:
1. Test temperature = room temperature (25
°
C)
2. P
INT
= I
DD
x V
DD
Watts (chip internal power)
Table 7.
Estimated Power Dissipation for Various Configurations
(1)
Bus (MHz)
CPM
Multiplier
Core CPU
Multiplier
CPM (MHz)
CPU (MHz)
P
INT
(W)
(2)
Vddl 1.8 Volts
Vddl 2.0 Volts
Nominal
Maximum
Nominal
Maximum
66.66
2
3
133
200
1.2
2
1.8
2.3
66.66
2.5
3
166
200
1.3
2.1
1.9
2.3
66.66
3
4
200
266
–
–
2.3
2.9
66.66
3
4.5
200
300
–
–
2.4
3.1
83.33
2
3
166
250
–
–
2.2
2.8
83.33
2
3
166
250
–
–
2.2
2.8
83.33
2.5
3.5
208
291
–
–
2.4
3.1
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