參數(shù)資料
型號(hào)： PC56F8006VLF
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 29/106頁(yè)
文件大?。?/td> 0K
描述： DSP 16BIT 48-LQFP
標(biāo)準(zhǔn)包裝： 250
系列： 56F8xxx
核心處理器： 56800
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，LIN，SCI，SPI
外圍設(shè)備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 40
程序存儲(chǔ)器容量： 16KB（8K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1K x 16
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 24x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 48-LQFP
包裝： 托盤(pán)
Memory Maps
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
29
5
Memory Maps
5.1
Introduction
The 56F8006/56F8002 device is based on the 56800E core. It uses a dual Harvard-style architecture with two independent
memory spaces for Data and Program. On-chip RAM is shared by both data and program spaces and flash memory is used only
in program space.
This section provides memory maps for:
Program address space, including the interrupt vector table
Data address space, including the EOnCE memory and peripheral memory maps
On-chip memory sizes for the device are summarized in Table 6. Flash memories’ restrictions are identified in the “Use
Restrictions” column of Table 6.
5.2
Program Map
The 56F8006/56F8002 series provide up to 16 KB on-chip flash memory. It primarily accesses through the program memory
buses (PAB; PDB). PAB is used to select program memory addresses; instruction fetches are performed over PDB. Data can be
read and written to program memory space through primary data memory buses: CDBW for data write and CDBR for data read.
Accessing program memory space over the data memory buses takes longer access time compared to accessing data memory
space. The special MOVE instructions are provided to support these accesses. The benefit is that non time critical constants or
tables can be stored and accessed in program memory.
The program memory map is shown in Table 7 and Table 8.
Table 6. Chip Memory Configurations
On-Chip Memory
56F8006
56F8002
Use Restrictions
Program Flash
(PFLASH)
8K x 16
or
16 KB
6K x 16
or
12 KB
Erase/program via flash interface unit and word writes to CDBW
Unified RAM (RAM)
1K x 16
or
2 KB
1K x 16
or
2 KB
Usable by the program and data memory spaces
Table 7. Program Memory Map1 for 56F8006 at Reset
1 All addresses are 16-bit word addresses.
Begin/End Address
Memory Allocation
P: 0x1F FFFF
P: 0x00 8800
RESERVED
P: 0x00 83FF
P: 0x00 8000
On-Chip RAM2: 2 KB
2 This RAM is shared with data space starting at address X: 0x00 0000; see Figure 8.
P: 0x00 7FFF
P: 0x00 2000
RESERVED
P: 0x00 1FFF
P: 0x00 0000
Internal program flash: 16 KB
Interrupt vector table locates from 0x00 0000 to 0x00 0065
COP reset address = 0x00 0002
Boot location = 0x00 0000
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