參數(shù)資料
型號(hào)： PC33926PNB
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 5.0 A Throttle Control H-Bridge
中文描述： 5.0甲節(jié)氣門控制H橋
文件頁(yè)數(shù)： 8/24頁(yè)
文件大?。?/td> 378K
代理商： PC33926PNB
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
33926
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 8.0 V
≤
V
PWR
≤
28 V, -
40
°
C
≤
T
A
≤
125
°
C, GND = 0 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at T
A
= 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
PWM Frequency
(21)
f
PWM
f
MAX
t
D
ON
–
–
20
kHz
Maximum Switching Frequency During Current Limit Regulation
(22)
–
–
20
kHz
Output ON Delay
(23)
V
PWR
= 14 V
Output OFF Delay
(23)
V
PWR
= 14 V
I
LIM
Output Constant-OFF Time
(24)
I
LIM
Blanking Time
(25)
Disable Delay Time
(26)
–
–
18
μ
s
t
D
OFF
–
–
12
μ
s
t
A
t
B
15
20.5
32
μ
s
12
16.5
27
μ
s
t
DDISABLE
t
F
, t
R
–
–
8.0
μ
s
Output Rise and Fall Time
(27)
SLEW = SLOW
SLEW = FAST
Short Circuit Overtemperature Turn-OFF (Latch-OFF) Time
(28)
(29)
Power-ON Delay Time
(29)
Output MOSFET
Body Diode Reverse Recovery Time
(29)
Charge Pump Operating Frequency
(29)
1.5
0.5
3.0
–
8.0
1.45
μ
s
t
FAULT
t
POD
t
R R
f
CP
–
2.0
–
μ
s
–
1.0
5.0
ms
ns
75
100
150
–
7.0
–
MHz
Notes
21.
The maximum PWM frequency is obtained when the device is set to Fast Slew Rate via the SLEW pin. PWM-ing when SLEW is set to
SLOW should be limited to frequencies < 11 kHz in order to allow the internal high-side driver circuitry time to fully enhance the high-side
MOSFETs.
The internal current limit circuitry produces a constant-OFF-time Pulse Width Modulation of the output current. The output load’s
inductance, capacitance, and resistance characteristics affect the total switching period (OFF-time + ON-time), and thus the PWM
frequency during current limit.
*
Output Delay is the time duration from 1.5V on the IN1 or IN2 input signal to the 20% or 80% point (dependent on the transition direction)
of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from 1.5V on the input signal to the 80% point of the
output response signal. If the output is transitioning LOW-to-HIGH, the delay is from 1.5V on the input signal to the 20% point of the output
response signal. See
Figure 4
, page
9
.
The time during which the internal constant-OFF
time PWM current regulation circuit has tri-stated the output bridge.
The time during which the current regulation threshold is ignored so that the short-circuit detection threshold comparators may have time
to act.
*
Disable Delay Time measurement is defined in
Figure 5
, page
9
.
Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal with V
PWR
= 14 V,
R
LOAD
= 3.0 ohm. See
Figure 6
, page
9
.
Load currents ramping up to the current regulation threshold become limited at the I
LIM
value (see
Figure 7
). The short circuit currents
possess a di/dt that ramps up to the I
SCH
or I
SCL
threshold during the I
LIM
blanking time, registering as a short circuit event detection and
causing the shutdown circuitry to force the output into an immediate tri-state latch-OFF (see
Figure 8
). Operation in
Current Limit mode
may cause junction temperatures to rise. Junction temperatures above ~160
°
C will cause the output current limit threshold to “fold back”,
or decrease, until ~175
°
C is reached, after which the T
LIM
thermal latch-OFF will occur. Permissible operation within this fold back region
is limited to non-repetitive transient events of duration not to exceed 30 seconds (see
Figure 9
).
Parameter is Guaranteed By Design.
22.
23.
24.
25.
26.
27.
28.
29.
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