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參數(shù)資料
| 型號： | PC-COM4 |
| 英文描述： | PC(ISA)BUS I/O CARD |
| 中文描述： | 電腦（ISA）總線的I / O卡 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大小： | 492K |
| 代理商： | PC-COM4 |
Page 3
2192-09197-000-000
J606 PC-COM4
CONTROL SYSTEMS
The option link LK34 defines the addressing mode for channels A and B, and channels C & D
as follows:
Additionally, LK31 can be used to disable any channel from being addressed by removing the
appropriate link A, B, C or D.
Each channel occupies 8 bytes of I/O space with the following registers defined:
Interrupts
Four links, LK28-30,33 define the interrupt mapping for each of channels A to D respectively.
Each channel can be connected to any of IRQ3, 4, 5, 7, 9, 10, 11, 12 or 15. Note that IRQ10,
11, 12 and 15 are only available when the PC-COM4 is used in a 16 bit ISABUS slot.
If any of links LK28-30,33 is fitted in the OR position, then this channels interrupt is ORed to
link LK35 which can then be connected to any of the above IRQ lines. This permits all of the
UARTs on the PC-COM4 to share a single interrupt line to conserve IRQ resources.
LK34 – Option Link
CD0
X
X
X
X
Omit
Fit
Omit +
Fit
Channel Address Mapping
Chan A
Chan B
COM1
COM2
COM 2
COM 3
COM 3
COM 4
Variable Base Address
X
X
X
X
X
X
X
X
CD1
X
X
X
X
Omit
Omit
Fit +
Fit
AB1
Omit
Omit
Fit
Fit +
X
X
X
X
AB0
Omit
Fit
Omit
Fit +
X
X
X
X
Chan C
X
X
X
X
COM 1
COM 2
COM 3
Variable Base Address
Chan D
X
X
X
X
COM 2
COM 3
COM 4
Register Offset
General Register Set (DLAB[ICR:7]clear)
0
1
2
3
4
5
6
7
Baud Rate Register Set (DLAB[ICR:7]set)
0
1
Mnemonic
Read Register
Write Register
RHT/THR
IER
ISR/FCR
LCR
MCR
LSR
MSR
SCR
Receive holding register
Transmit Holding Register
Interrupt Enable Register
Interrupt Status Register
FIFO Control Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratchpad Register
DLL
DLM
LSB of Divisor Latch
MSB of Divisor Latch
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