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參數(shù)資料
| 型號(hào)： | P90CL301 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low voltage 16-bit microcontroller |
| 中文描述： | 低電壓16位微控制器 |
| 文件頁(yè)數(shù)： | 41/92頁(yè) |
| 文件大?。?/td> | 526K |
| 代理商： | P90CL301 |
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1996 Dec 11
41
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 54
Function of UART queue registers
Notes
1.
2.
3.
UQRC and UQTC can be accessed together as a word or as two bytes.
For each byte transmitted the UQTA is incremented, the UQTS is decremented.
For each byte received the UQRA is incremented, the UQRS is decremented.The CPU can read this register on the
fly, but in this case the accuracy is not guaranteed so it is recommended to halt the queue and read the values.
NAME
UQRC
(1)
UQTC
(1)
FUNCTION
DESCRIPTION
SIZE
Reception Control Register
Transmission Control Register
and Interrupt Flags.
Transmit Buffer Address Register
Reception control and status flags.
Transmission control and status flags and interrupt flags.
byte
byte
UQTA
(2)
Start address of transmission buffer from 00H to FFH,
corresponds to CPU address from FFFF 9000H to
FFFF 90FFH.
Size of the transmission buffer. Limited to 256 bytes.
byte
UQTS
(2)
Transmit Buffer Size Register
UQRA
(3)
Reception Buffer Address Register Start address of reception buffer from 00H to FFH,
corresponds to CPU address from FFFF 9000H to
FFFF 90FFH.
UQRS
(3)
Reception Buffer Size Register
Size of the reception buffer. Limited to 256 bytes.
UQRM
Reception Match Register
The received characters are compared with the value
contained in this register and an interrupt is generated when
they are equal.
byte
byte
byte
byte
Fig.12 UART queue block diagram.
handbook, full pagewidth
UQTS
UQRS
DECR
zero
MGD782
data bus
address bus
ten
UQRC
UQTC
UART QUEUE CONTROL
UQRM
SCON0
TI
TX
data bus
RX
RIF
TIF
RI
MUX
MUX
MUX
TX SBUF0
RX SBUF0
RAM
256 BYTES
INCR
=
UQRA
UQTA
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