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參數(shù)資料
| 型號： | P90CL301 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low voltage 16-bit microcontroller |
| 中文描述： | 低電壓16位微控制器 |
| 文件頁數(shù)： | 13/92頁 |
| 文件大?。?/td> | 526K |
| 代理商： | P90CL301 |
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1996 Dec 11
13
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 15
Selection of prescaler divisor values
PCLK3
PCLK1
PCLK0
DIVISOR (D)
DIVISOR FOR UART IN MODE 0
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
2
3
4
6
6
6
6
12
12
12
5 (default value after a CPU reset)
6
8
10
6.5
Reset operation
The reset circuitry of the P90CL301BFH is connected to
the pins RESET, HALT, RESETIN and to the internal
Watchdog Timer. A Schmitt trigger is used at the input pin
for noise rejection. After Power-on a CPU reset is
accomplished by holding the RESET pin and the HALT pin
LOW for at least 50 oscillator clocks after the oscillator has
stabilized.
For further information on the clock generation, see
Section 6.6. The CPU responds by reading the reset
vectors; the long word at address 000000H is loaded into
the Supervisor stack and the long word data at address
000004H is loaded into the program counter PC. The
interrupt level is set to 7 in the Status Register and
execution starts at the PC location. By pulling the RESET
pin LOW and keeping HALT HIGH, only the peripherals
are reset.
When V
DD
is turned on and its rise time does not exceed
10 ms, an automatic reset can be performed by
connecting the RESETIN pin to V
DD
via an external
capacitor. The external capacitor is charged via an internal
pull-down resistor.
The RESET pin can also be pulled LOW internally by a
pull-down transistor activated by an overflow of the
Watchdog Timer. When the CPU executes a RESET
instruction, the RESET pin is pulled LOW. When the CPU
is internally halted (at double bus fault), the HALT pin is
pulled LOW and only a CPU reset can restart the
processor.
The internal signal RESET_AS (Reset Asynchronous)
resets the core and all registers.
When an internal Watchdog Timer overflow occurs, an
internal CPU reset is generated which resets all registers
except the SYSCON, PCON, PRL and PRH registers and
pulls the RESET pin LOW during 12 clock cycles.
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